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hdl
网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。(a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong.
tested.)
- 2009-03-31 22:36:37下载
- 积分：1
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greedy_snake
基于Basys2开发板实现VGA输出，PS/2键盘接入的贪吃蛇游戏，键盘上下左右控制方向，小键盘+键控制速度，小键盘回车开始游戏，空格暂停游戏。(Basys2 based development board to achieve VGA output, PS/2 keyboard access Snake game, up and down the keyboard to control the direction, speed control keypad+ key keypad Enter to start the game, pause the game space.)
- 2021-03-27 17:09:12下载
- 积分：1
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dot_product
实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)
- 2015-01-27 10:52:52下载
- 积分：1
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TechAss-2006
un controller pi par le langage VHDL xilinx ise design 13.2
- 2013-12-16 22:53:24下载
- 积分：1
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基于FPGA的FFT算法的设计与实现
基于FPGA实现FFT算法，内容包含论文、程序、仿真等等(Implementation of FFT algorithm based on FPGA)
- 2020-07-02 00:00:07下载
- 积分：1
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wishbone 源代码，opencore
wishbone 源代码，opencore-wishbone source code, opencore
- 2022-05-13 00:28:04下载
- 积分：1
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VHDL-Code-For-Full-Adder-By-Data-Flow-Modelling
VHDL Code For Full Adder By Data Flow Modelling
- 2013-11-08 00:39:04下载
- 积分：1
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openmips
一个开源mips处理器verilog 源码(wishbone interface wishbone interface)
- 2020-08-16 15:48:32下载
- 积分：1
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RS232 data transmitter, suitable for beginners VHDL reference
RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
- 2022-03-15 09:13:00下载
- 积分：1
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Timing1111_Symcronization
使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过(Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by)
- 2021-05-07 14:28:36下载
- 积分：1
