openmips

代码说明：

  一个开源mips处理器verilog 源码(wishbone interface wishbone interface)

文件列表：

Chapter12
.........\cp0_reg.v,6710,2014-03-14
.........\ctrl.v,3645,2014-03-27
.........\defines.v,7634,2014-03-30
.........\div.v,4942,2014-03-02
.........\ex.v,18190,2014-03-16
.........\ex_mem.v,6211,2014-03-14
.........\hilo_reg.v,2491,2014-02-10
.........\id.v,30542,2014-05-12
.........\id_ex.v,4975,2014-03-14
.........\if_id.v,2685,2014-03-14
.........\LLbit_reg.v,2494,2014-03-07
.........\mem.v,14343,2014-07-31
.........\mem.v.bak,14190,2014-03-30
.........\mem_wb.v,4717,2014-03-29
.........\openmips.v,18239,2014-03-30
.........\pc_reg.v,2825,2014-03-30
.........\regfile.v,3386,2014-02-07
.........\wishbone_bus_if.v,5804,2014-03-31