ISE7.1，采用VIRTEX-II芯片。实现adc数据采样，平均，通道选择，采样时钟选择，数据格式调整，内含fifo,uart等模块。-ISE7.1, using VIRTEX-II chip. Adc realize data sampling, on average, channel selection, the sampling clock select, adjust data formats, including fifo, uart modules.

Ship navigation project

the 8 bit alu by verilog

all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display

verilog ADPLL file with testbench

说明：  RISC全部源码，包含仿真文件，使用makefile脚本编写，能通过vcs编译(RISC all source code, including simulation files, using makefile script, can be compiled through VCS)

Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.

新版 小米抢购器 -源码 已经测试，代码很有用，已经抢了好几个小米3了，希望对大家有用(The new millet to snap up- source Have test, the code is useful, has robbed several millet 3, hope useful for everyone)

非常优秀的国外VHDL设计教程，可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation

基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....