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verilog-lfsr-master
Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
- 2020-06-24 21:40:01下载
- 积分：1
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人脸识别（3D）
基于高清视频的3D人脸识别源代码，四万多行，经过FPGA实际验证，最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)
- 2019-07-01 16:22:46下载
- 积分：1
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pl_read_write_ps_ddr
说明： PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重，常常需要将 PL 端的大量数据实时送到 PS 端处理，或者将 PS 端处理结果实时送到 PL 端处理，但是各种协议非常麻烦，灵活性也比较差，直接通过 AXI 总线来读写 PS 端 ddr 的数据，这里面涉及到 AXI4 协议，vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分：1
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基于FPGA的串口通信程序设计
本代码是一个基于FPGA的串口通信程序设计，程序采用Verilog语言编写，工程中已经加入了仿真模型，并设置了仿真，如果你的电脑也安装了modelsim-altera，就可以直接点击RTL仿真，就能出仿真结果了。程序的主要功能实串口测试，当FPGA芯片收到上位机发送的数据时将数据再发回到上位机，在串口助手上进行显示。
- 2022-03-22 10:58:18下载
- 积分：1
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4 位超前进位加法器的设计
本文阐述了设计的 4 位携带看前方 adder.this 加法器是比较会波及进位加法器的高速度。
- 2022-03-24 06:33:28下载
- 积分：1
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verilog编写的1024点的fft快速傅立叶变换代码
verilog编写的1024点的fft快速傅立叶变换代码
- 2023-03-30 03:00:03下载
- 积分：1
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SPI_UVM_VIP
说明： SPI协议的芯片验证VIP,用UVM搭建平台验证代码(Chip verification VIP of SPI protocol, build platform verification code with UVM)
- 2020-08-25 09:58:15下载
- 积分：1
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jiaotongled
该源码用vhdl语言制作了一个简单的交通灯，方便大家学习~~(The source vhdl language produced by a simple traffic light, facilitate learning ~ ~)
- 2010-11-20 14:44:36下载
- 积分：1
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complex_timing_by_Primetime
用PrimeTime的技巧，解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)
- 2012-08-05 19:07:47下载
- 积分：1
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FPGA-design-
FPGA设计的四种常用思想与技巧分享:串并转换设计技巧、流水线设计思想……(FPGA design of four common ideas and techniques)
- 2013-05-22 22:55:38下载
- 积分：1
