登录
首页 » VHDL » 基于FPGA的电子时钟设计

基于FPGA的电子时钟设计

于 2022-11-29 发布 文件大小:2.10 MB
0 50
下载积分: 2 下载次数: 1

代码说明:

具体设计内容计时功能:电子表的基本功能,要求用LCD显示,显示格式是时、分、秒;校时功能:用户可以更改当前时间。设置闹钟时间:用户可以设置闹钟时间,其操作过程与校时过程一样;整点报时开关:整点报时可以由用户设定为开启或关闭两种状态,当整点报时开启时,电子表会在整点时发出1秒的闹铃声(在UP3的板上用一个LED表示);闹钟功能开关:闹钟由用户设定为开启或关闭,当闹钟开关开启时,如果当前时间与设置的闹钟时间一致,发出长达10秒的闹铃声;

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • FPGA verilog代码
    说明:  数电实验FPGA verilog代码,包括秒表、全加器、半加器等。(FPGA Verilog code for digital experiment)
    2020-04-29 11:16:05下载
    积分:1
  • vhdl
    vhdl
    2022-06-20 13:51:22下载
    积分:1
  • codic
    8级cordic 算法verilog (8 cordic algorithm verilog)
    2013-08-21 11:31:46下载
    积分:1
  • 4x4-Keypad
    fpga的一个小程序用于3s500e 4*4键盘模块(fpga is a small program used 3s500e 4* 4 keyboard module)
    2013-07-21 11:41:36下载
    积分:1
  • 我用VHDL写的正弦,用FPGA内部ROM,有仿真testbench,在quartus里可以运行。在板子里已经验证...
    我用VHDL写的正弦,用FPGA内部ROM,有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
    2022-07-25 14:12:00下载
    积分:1
  • which I have recently bought a CPLD Development Board VHDL source code accompani...
    这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
    2022-02-20 05:51:18下载
    积分:1
  • control_s
    数控机床 多轴插补原理积分算法,实现s曲线加减速原理(Numerical control machine tool multi axis interpolation principle, integration algorithm, to achieve the S curve acceleration and deceleration principle)
    2021-05-07 09:58:36下载
    积分:1
  • ddr_for_controller_and_phy
    说明:  这是本人曾经参与的一个DDR controller接口项目,主要是FPGA rtl实现,仅供参考。(This is a DDR controller interface project that I once participated in, mainly implemented by FPGA RTL, for reference only.)
    2020-12-21 20:59:08下载
    积分:1
  • 浅显易懂的vrilogHDL的程序,可以帮助你迅速上手
    浅显易懂的vrilogHDL的程序,可以帮助你迅速上手-Easy and simple VerilogHDL programs to help you to get to the language quickly.
    2022-03-05 20:26:55下载
    积分:1
  • fir48
    48阶FIR设计,采用VHDL语言描述,门级映射……(48-oders FIR design with VHDL language and gate level)
    2021-04-14 19:38:55下载
    积分:1
  • 696518资源总数
  • 104305会员总数
  • 11今日下载