ddr_for_controller_and_phy

代码说明：

说明：  这是本人曾经参与的一个DDR controller接口项目，主要是FPGA rtl实现，仅供参考。(This is a DDR controller interface project that I once participated in, mainly implemented by FPGA RTL, for reference only.)

文件列表：

ddr_for_controller_and_phy\addr_gen_16bit_00 - 副本 (2).v, 6198 , 2015-02-09
ddr_for_controller_and_phy\addr_gen_16bit_00 - 副本.v, 5573 , 2015-02-05
ddr_for_controller_and_phy\addr_gen_16bit_00.v, 6504 , 2015-02-13
ddr_for_controller_and_phy\addr_gen_16bit_00_4units.v, 5719 , 2015-02-11
ddr_for_controller_and_phy\addr_gen_16bit_00_mody - 副本.v, 6199 , 2015-02-10
ddr_for_controller_and_phy\addr_gen_16bit_00_mody.v, 6426 , 2015-02-11
ddr_for_controller_and_phy\addr_gen_16bit_00_ok16.v, 6757 , 2015-02-13
ddr_for_controller_and_phy\addr_gen_16bit_00_ok20.v, 6519 , 2015-02-12
ddr_for_controller_and_phy\addr_gen_16bit_00_ok32.v, 6490 , 2015-02-12
ddr_for_controller_and_phy\cal_ctl.v, 19111 , 2015-02-04
ddr_for_controller_and_phy\cal_top.v, 2040 , 2015-02-04
ddr_for_controller_and_phy\clk_dcm.v, 4664 , 2015-02-04
ddr_for_controller_and_phy\cmd_fsm.v, 11694 , 2015-02-04
ddr_for_controller_and_phy\cmp_data_16bit.v, 2856 , 2015-02-09
ddr_for_controller_and_phy\controller_16bit_00.v, 60251 , 2015-02-11
ddr_for_controller_and_phy\controller_iobs_16bit_00.v, 8613 , 2015-02-05
ddr_for_controller_and_phy\data_path_16bit_rl.v, 6125 , 2015-02-05
ddr_for_controller_and_phy\data_path_iobs_16bit.v, 10487 , 2015-02-05
ddr_for_controller_and_phy\data_path_rst.v, 1376 , 2015-02-04
ddr_for_controller_and_phy\data_read_16bit_rl.v, 20329 , 2015-02-04
ddr_for_controller_and_phy\data_read_controller_16bit_rl.v, 13596 , 2015-02-04
ddr_for_controller_and_phy\data_write_16bit.v, 3463 , 2015-02-04
ddr_for_controller_and_phy\ddr1_dm_16bit.v, 4058 , 2015-02-04
ddr_for_controller_and_phy\ddr1_test_16bit_00.v, 7667 , 2015-02-09
ddr_for_controller_and_phy\ddr1_test_bench_16bit_00.v, 9858 , 2015-02-10
ddr_for_controller_and_phy\ddr1_top_16bit_00.v, 9493 , 2015-02-05
ddr_for_controller_and_phy\ddr_dqs_iob.v, 4353 , 2015-02-04
ddr_for_controller_and_phy\ddr_dq_iob.v, 4726 , 2015-02-04
ddr_for_controller_and_phy\dqs_delay.v, 3984 , 2015-02-04
ddr_for_controller_and_phy\fifo_0_wr_en.v, 695 , 2015-02-04
ddr_for_controller_and_phy\fifo_1_wr_en.v, 792 , 2015-02-04
ddr_for_controller_and_phy\infrastructure.v, 1135 , 2015-02-04
ddr_for_controller_and_phy\infrastructure_iobs_16bit.v, 1965 , 2015-02-04
ddr_for_controller_and_phy\infrastructure_top.v, 5635 , 2015-02-04
ddr_for_controller_and_phy\iobs_16bit_00.v, 5764 , 2015-02-05
ddr_for_controller_and_phy\lfsr32_16bit.v, 3508 , 2015-02-10
ddr_for_controller_and_phy\mem_interface_top.v, 4421 , 2015-02-05
ddr_for_controller_and_phy\mybufg.v, 310 , 2015-02-04
ddr_for_controller_and_phy\parameters_16bit_00.v, 461 , 2015-02-04
ddr_for_controller_and_phy\rd_gray_cntr.v, 1777 , 2015-02-04
ddr_for_controller_and_phy\tap_dly.v, 8334 , 2015-02-04
ddr_for_controller_and_phy\virtex2.v, 318895 , 2015-02-04
ddr_for_controller_and_phy\wr_gray_cntr.v, 1862 , 2015-02-04
ddr_for_controller_and_phy, 0 , 2020-02-24