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4x4-Keypad
fpga的一个小程序用于3s500e 4*4键盘模块(fpga is a small program used 3s500e 4* 4 keyboard module)
- 2013-07-21 11:41:36下载
- 积分:1
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blessing3.9.6
Blessing_3_v3_9_6稳定盈利set,仅限AUDNZD货币对,周期M1。
使用本压缩包内的SET,LAF默认是15,根据历史测试来看具有较大的风险,需要手动规避数据。
合理设置为LAF=8,请自行设置和调试,找到自己合适的风险值。
(Blessing_3_v3_9_6 stable profit set, only AUDNZD currency pairs, cycle M1.
Use this package in the SET, the default is 15 fans, according to the angles of history test has great risk, need to avoid data manually.
Reasonable set to fans = 8, please make your own setting and debugging, find their proper risk value.)
- 2015-04-15 22:45:03下载
- 积分:1
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wishbone
wishbone接口的设计,在交换机和MAC之间建立wishbone接口(the wishbone interface design, wishbone interface between the switch and MAC)
- 2012-12-05 12:22:24下载
- 积分:1
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QAM_verilog
基于FPGA的16QAM,用verilog编写,其中DDS为自己编写,含设计文件和testbench。已通过moldesim软件仿真。 (FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.)
- 2021-02-22 18:29:41下载
- 积分:1
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SRAM完整实现——verilog语言
本代码基于Xilinx FPGA开发平台,采用Verilog语言编写,完整SRAM所有功能。已经过测试验证。
- 2023-06-19 17:40:03下载
- 积分:1
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MIT_Press_Circuit_Design_with_VHDL_(2004)
circuit design with VHDL e-book MIT Press....
- 2009-05-08 00:33:54下载
- 积分:1
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18B20PLCD
温度液晶显示演示程序
LCD数据线:P0口
LCD控制线:RS P20 RW P21 E P22 BUSY P07
18B20端口DQ :P27
(Temperature of liquid crystal display demo
Data line: P0 LCD
LCD RS P20 RW P21 control line: E P22 BUSY P07
18B20 DQ : P27 port
)
- 2011-12-03 23:04:34下载
- 积分:1
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2010_5
PI控制器的算法及源码,迅速掌握FPGA的VHDL算法实现!(Algorithm and source code of PI controller, quickly grasp the implementation of VHDL algorithm in FPGA!)
- 2014-07-04 15:25:59下载
- 积分:1
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FIFO_Buffer(verilog)
这是一个FIFO_Buffer的verilog代码.(This is a FIFO_Buffer the Verilog code.)
- 2021-04-22 13:38:49下载
- 积分:1
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mul_ser12
本源码是用Verilog编写的12位移位相加乘法器的设计源码,开发软件为MAX+PLUS,已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)
- 2011-05-31 14:19:30下载
- 积分:1