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gtx_aurora_zc706_clock_module
对aurora模块时钟处理模块，实现时钟的分频等处理(Aurora module clock processing module,Clock frequency division and other processing)
- 2018-01-23 09:03:31下载
- 积分：1
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vhdl um teste com muita coisa interessante ae pra ver
vhdl um teste com muita coisa interessante ae pra ver
- 2023-07-05 20:40:02下载
- 积分：1
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Vhdl实现的鼠标协议历程，代码可读性高，适合作为案例参考。
Vhdl实现的鼠标协议历程，代码可读性高，适合作为案例参考。-VHDL realize the course of the mouse protocol, code readable, suitable as a reference case.
- 2023-05-02 16:50:03下载
- 积分：1
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reversible-squarer
it is hybrid squarer circuit which will be designed using reversible gates which having les hardware complexity with compared to the conventional gates
- 2015-04-21 15:05:54下载
- 积分：1
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基于FPGA的实现小数倍分频代码，广泛应用于数字通信中。
基于FPGA的实现小数倍分频代码，广泛应用于数字通信中。-FPGA-based implementation of a small multiple of sub-frequency code, widely used in digital communications.
- 2022-04-19 03:39:18下载
- 积分：1
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rs_204_188----v1.0
RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；(RS Coding and Decoding Verilog code， implement RS（204,188) )
- 2021-03-25 20:29:14下载
- 积分：1
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JOP kernel source code cache, not easy to find, we must kits
JOP的内核缓存源码，不易找到，大家一定要顶啊-JOP kernel source code cache, not easy to find, we must kits
- 2022-01-27 18:39:54下载
- 积分：1
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此程序用通过PFGA用VHDL语言实现了傅立叶变换，希望对大家有用...
此程序用通过PFGA用VHDL语言实现了傅立叶变换，希望对大家有用
- 2022-06-25 23:29:26下载
- 积分：1
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uart
UART串口的verilog源代码，完全正确...........(UART serial Verilog source code, completely correct ...........)
- 2009-03-02 14:44:16下载
- 积分：1
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Six-phase-Motor-Based-on-DSP
说明： 设计了六相感应电机的控还原
制平台的硬件结构及其各个组成部分,控制平台结构主要由DSP控制系统和主驱动电路系统以及检测电路系统组成。控制系统采用TI公司的TMS320F2812快速DSP控制芯片。
(This paper designs the hardware structure of the six-phase motor control system and introduces every component. The control platform consists of DSP control system, main drive circuit system and detection circuit system .The control system adopts TMS320F2812 DSP chip of TI Company. 更多还原
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- 2011-03-01 12:08:36下载
- 积分：1
