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Description Sramoc (K, M) said the figures used in 0,1,2 ..., K
描述
Sramoc ( K , M ) 表示用数字0、1、2…、K-1组成的自然数中能被M整除的最小数。给定 K、M，求Sramoc ( K,M )。例如 K=2，M=7的时候，Sramoc( 2 , 7 ) = 1001。
输入
第一行为两个整数K、M满足2
- 2022-05-25 16:18:18下载
- 积分：1
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cic_4_dec
实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波(Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter)
- 2008-07-08 16:23:03下载
- 积分：1
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lab_instructions3
The objective of the labs today is to give you a basic understanding of FPGA design and
enough experience to begin your own FPGA design with the ISE 10.1 tools and the
Xilinx Spartan-3A DSP 1800A Starter Kit.
- 2010-12-31 17:16:42下载
- 积分：1
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fpga
verilg语言实现测频 及与stm32以fsmc通信方式进行通信(Verilg to achieve frequency measurement and communication with STM32 in FSMC communication mode)
- 2017-07-27 20:05:25下载
- 积分：1
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fsk
基于FPGA的fsk调制程序，包括载波的生成，nco的设置(FPGA-based fsk modulation procedures, including carrier generation, nco settings)
- 2016-05-12 21:00:56下载
- 积分：1
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用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试...
用verilog HDL语言，通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试
-Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
- 2023-05-23 03:15:03下载
- 积分：1
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HDB3
用Verilog HDL语言进行HDB3编码，并通过Quartus Ⅱ仿真验证(With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ)
- 2020-11-30 11:19:28下载
- 积分：1
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数字信号处理的FPGA实现(第4版)源码
数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)
- 2021-01-16 23:08:50下载
- 积分：1
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time_frequency_analysis
一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)
- 2013-12-04 10:13:24下载
- 积分：1
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n_bit_counter
n bit generic shift registers
- 2011-03-18 17:55:19下载
- 积分：1
