-
tanchishe-QuartusII
VGA显示FPGA实现的VHDL语言的贪吃蛇游戏设计
本设计分为6个模块主要是扫描模块 VGA现实和控制模块 游戏设计的模块 电源模块等
用QUARTUS2仿真运行(VGA display FPGA VHDL language to realize the Snake game design
The design is divided into six modules mainly scanning module VGA module power module and control module reality game design, etc.
Simulation run with QUARTUS2)
- 2020-11-06 10:09:50下载
- 积分：1
-
delayline_b
基于延迟线的数字脉冲宽度调制，用于电力电子设备的触发信号产生(puls wide modulator based on delayline)
- 2015-03-10 15:45:01下载
- 积分：1
-
asynchronous reset state machine
异步复位状态机
-- State Machine with Asynchronous Reset
-- dowload from: www.fpga.com.cn & www.pld.com.cn
-asynchronous reset state machine-- State Machine with Asynchronou "s Reset-- dowload from : www.fpga.com.cn
- 2023-07-14 12:30:03下载
- 积分：1
-
breathingLED
stc12c5a60s2单片机做的两路呼吸灯，可以用ad和按键控制闪动频率(stc12c5a60s2 SCM done with the two breathing lights, you can use the ad and buttons to control the flashing frequency)
- 2013-05-10 15:33:18下载
- 积分：1
-
HDMI_FPGA
该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)
- 2020-12-17 11:09:12下载
- 积分：1
-
SASX
Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC
- 2020-06-24 11:40:02下载
- 积分：1
-
第7章数字系统设计实例
7.1 半整数分频器的设计
7.2 音乐发生器
7.3 2FSK/2PSK信号产生器
7.4 实用多功能电子表
7....
第7章数字系统设计实例
7.1 半整数分频器的设计
7.2 音乐发生器
7.3 2FSK/2PSK信号产生器
7.4 实用多功能电子表
7.5 交通灯控制器
7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-function electronic traffic signal controllers 7.5 7.6 Digital Cymometer
- 2022-04-12 22:39:11下载
- 积分：1
-
altera公司cpld的原理图库(protel格式)
altera公司cpld的原理图库(protel格式)-sch.lib about altera s cpld.
- 2022-03-18 02:53:20下载
- 积分：1
-
sha1
利用verilog语言实现了SHA-1机密算法，具体算法与加密芯片ds28e01一致。(Using Verilog to achieve the SHA-1 secret algorithm, the specific algorithm is consistent with the encryption chip ds28e01.)
- 2020-11-08 08:49:47下载
- 积分：1
-
AD_TO_FIFO
A/D采集的数据缓存进入fifo，并通过读信号将FIFO中的数据送入网口(A/D sample data buffer to fifo,and then read enable to ethernet.)
- 2020-07-10 21:08:54下载
- 积分：1
