-
SDR
直接序列扩频通信的Verilog仿真代码，在Quartus II中实现。(Direct sequence spread spectrum communication Verilog simulation code, implemented in Quartus II.)
- 2011-01-16 12:18:18下载
- 积分：1
-
FIFO_UVM_VIP
用uvm验证方法学验证异步fifo，文件包括异步FIFOrtl代码和uvm组件(Verification of asynchronous FIFO with UVM)
- 2021-04-28 09:48:44下载
- 积分：1
-
can_exm1_sys
CAN总线的数据采集，FPGA到USB。verilog hdl语言。(CAN bus data acquisition, FPGA to the USB. verilog hdl language.)
- 2013-05-31 15:01:11下载
- 积分：1
-
The_entire_FPGA_design_flow_Modelsim_Synplify
详细的说明了FPGA设计的整个流程
FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)
- 2009-04-06 10:12:48下载
- 积分：1
-
verilog实现qdpsk调制解调
实现qpsk解码，适合新手学习，代码简单，好用(mplementation of QPSK decoding)
- 2018-11-16 23:36:38下载
- 积分：1
-
vivado2019d1license
说明： vivado的license ,可以用在2019.1,2019.2,在win10 64bit上已检验过.(It can used in vivado2019.1,2019.2)
- 2020-03-21 17:15:21下载
- 积分：1
-
S03_基于ZYNQ的DMA与VDMA的应用开发
VIVADO dma以及vdma 使用文档 基于ZYNQ 7020(vivado DMA&VDMA example text of zynq)
- 2020-06-17 11:40:02下载
- 积分：1
-
W5100
使用spi模式初始化w5100，实现了快速以太网的初步建立(Using the spi mode initialization w5100, to achieve the initial establishment of a Fast Ethernet)
- 2020-08-02 20:08:35下载
- 积分：1
-
bubblesort
根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果，含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)
- 2021-05-08 13:28:35下载
- 积分：1
-
PipelineSim
一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)
- 2012-06-24 22:19:14下载
- 积分：1
