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useful VHDL document for programmer
useful VHDL document for programmer
- 2022-02-28 15:00:15下载
- 积分：1
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Uart2Sdram2TFT_median_filter
说明： 使用FPGA实现中值滤波算法，能够使数据直接使用该系统对数据进行中值滤波。(FPGA is used to realize the median filtering algorithm, which can make the data directly use the system for median filtering.)
- 2019-12-30 21:27:58下载
- 积分：1
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Cordic_matlab
实现自然对数运算的cordic算法的matlab浮点仿真，以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)
- 2013-11-01 15:10:09下载
- 积分：1
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dw_ahb_dmac_db
It is Synopsys dmac controller databook
- 2020-10-10 10:27:34下载
- 积分：1
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show frequency measurement, external 24MHz crystal oscillator, the data show tha...
显示频率测量，外接24MHz晶振，显示数据为三位，分四个档来测量-show frequency measurement, external 24MHz crystal oscillator, the data show that three, four hours to measure stalls
- 2022-03-16 13:33:43下载
- 积分：1
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i2c
说明： 本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准，以主机模式与外围设备进行数据通信，对IIC从机模型进行读/读，读/写，写/写，写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失，自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection)
- 2019-06-18 12:18:10下载
- 积分：1
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ISE
设计一4位比较器,画出门级电路图,用verilog语言完成设计。
(Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )
- 2015-12-11 21:16:12下载
- 积分：1
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du to fpga 4*4 keyscan verilog
基于fpga的4*4键盘扫描verilog程序-du to fpga 4*4 keyscan verilog
- 2022-01-25 20:49:28下载
- 积分：1
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mimo_dectection
mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过
(mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on)
- 2021-02-15 12:09:48下载
- 积分：1
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CCSDS预测编码
最新的CCSDS高光谱图像压缩算法标准的FPGA实现，用VHDL实现的。可参考。绝对物有所值，希望对你的设计有所帮助!
- 2022-04-18 02:18:29下载
- 积分：1
