-
MX25L6445E--Verilog--v1.18
MX25L6445E开发时间，Verilog语言(MX25L6445E development time, Verilog language)
- 2011-07-20 15:11:31下载
- 积分：1
-
一个4×4矩阵键盘接口程序的Verilog设计（FPGA）
一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
- 2022-07-24 14:37:13下载
- 积分：1
-
Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！...
Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
- 2022-03-18 22:36:54下载
- 积分：1
-
本文件是用CPLD（EPM7064）驱动线阵CCD（ILX509），其中包括原理图和程序...
本文件是用CPLD（EPM7064）驱动线阵CCD（ILX509），其中包括原理图和程序-This document is a CPLD (EPM7064) driver line array CCD (ILX509), including schematics and procedures
- 2022-02-12 02:58:13下载
- 积分：1
-
sgiarcs
ARC firmware interface defines.
- 2015-06-27 18:50:37下载
- 积分：1
-
脉冲多普勒雷达回波信号相干积累的VHDL源程序
脉冲多普勒雷达回波信号相干积累的VHDL源程序-pulse Doppler radar echo signal coherent accumulation of VHDL source
- 2022-12-08 18:50:02下载
- 积分：1
-
FPGA使用Xilinx复位
Xilinx FPGA reset usage
- 2022-02-01 16:18:58下载
- 积分：1
-
SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
-
tcp_ip_core_w_dhcp_latest.tar
以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
- 2018-08-23 14:35:01下载
- 积分：1
-
位同步例程源代码,FPGA应用领域，Verilog
位同步例程源代码,FPGA应用领域，Verilog-Bit synchronization routines source code, FPGA applications, Verilog
- 2022-03-25 15:19:48下载
- 积分：1
