FPGA_UART
代码说明:
用Verilog语言实现的FPGA UART独立收发模块 思路简单,代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能:串口收到数据后立即回传,此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)
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