hssdrc IP核的可配置的通用SDRAM控制器的自适应银行…
于 2022-09-20 发布
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代码说明：
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License
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