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frequency-digital-phase-measuring-
低频数字式相位测量仪，数码管显示相位差，精度为0.1(Low frequency digital phase measuring instrument, digital pipe display phase difference
)
- 2011-08-10 00:45:49下载
- 积分：1
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mimo_dectection
mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过
(mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on)
- 2021-02-15 12:09:48下载
- 积分：1
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CU设计
计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计计算机组成原理CU设计
- 2023-06-25 08:00:03下载
- 积分：1
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HB1
说明： 半带滤波器，用于sigma-delta DAC中的设计(Half-band filter for sigma-delta DAC design)
- 2020-12-23 10:29:06下载
- 积分：1
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CORDIC_ATAN
FPGA实现反正切功能，工程原件，包括测试文件，能够很好实现该功能(FPGA implements arctangent function, original engineering)
- 2018-11-06 15:25:26下载
- 积分：1
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半加器
半加器
- 2022-10-16 16:40:03下载
- 积分：1
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基于 FPGA 的乒乓游戏
该项目实现了在Altera FPGA中的乒乓球比赛。游戏控制器是建立在FPGA中。玩家使用它连接到FPGA开发板玩的游戏键盘。本场比赛显示VGA屏幕上。所有部件，如键盘，VGA屏幕是由控制装置控制。
- 2022-03-28 19:03:27下载
- 积分：1
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Dual-Mode-Dual-Band-Filters
本文介绍一种波导双模双带滤波器的设计方法。(This paper presents a new class of dual-mode dualband
filters in which each polarization is dedicated to a selected
band. The equivalent circuit is a parallel combination of two inline
networks that represent each polarization. A transmission zero is
generated between the two bands by properly adjusting the relative
orientations of the input and output coupling apertures.)
- 2013-03-12 18:08:33下载
- 积分：1
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本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。...
本文件解压后clock_time.vhd采用编程环境maxplusII，完成时间秒定时、记时，设置时间秒、声光报警等功能。-this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
- 2022-07-03 03:02:23下载
- 积分：1
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usbd_ucos
说明： 基于ALINX AX7020硬件平台的USB-OTG通信程序。操作系统采用uCOS III v1.41，基本实现了双向USB2.0 块传输（Bulk Transfer）通信，zynq的PS端接收USB数据并回传至主机。经测试，主机端Window10系统采用libUSBK编程时，采用64字节的块时，传输速率可达210Mbps。zynq开发工具为Vivado2015.4，程序包中包含了全部的硬件和软件工程文档。(A USB-OTG communication project where an AX7020 platform is employed as USB device. The embeded operating system is uCOS III of version 1.41, and the FPGA toolchain is Vivado 2015.4. This project implements a full speed bidirectional USB2.0 bulk transfer. A test on Windows 10 host with libUSBK shows that the transfer speed is up to 201Mbps.)
- 2020-09-09 09:38:02下载
- 积分：1
