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add16
designing of 16 bit adder using 4 bit adder using verilog code
- 2012-09-10 14:40:32下载
- 积分：1
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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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uart_test
说明： 用于实现上位机与下位机之间通过RS232协议来进行通讯。(It is used to realize communication between upper computer and lower computer through RS232 protocol.)
- 2019-03-13 14:15:24下载
- 积分：1
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svpwm3
基於空間向量調變的開關法，在於載波做比較切出方波再送至開關讓馬達啟動(Based on the switching method of space vector modulation, the square wave is cut out for carrier comparison and sent to the switch to start the moto)
- 2019-01-04 16:07:37下载
- 积分：1
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基于FPGA的数字频率计VHDL源码（精确到1.1hz至20.0mhz）
当时是用于课程设计而编写的代码，经过的运行没有错误。精确率很高。基于FPGA的数字频率计VHDL源码（精确到1.1hz至20.0mhz）
- 2022-02-14 20:48:42下载
- 积分：1
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vhdl经典源代码――时钟设计，入门者必须掌握
vhdl经典源代码――时钟设计，入门者必须掌握-vhdl classical source code-- Clock Design, beginners must master
- 2023-05-04 10:00:03下载
- 积分：1
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Vhdl实现计算exp功能 在apex20k上经过验证
Vhdl实现计算exp功能 在apex20k上经过验证-Vhdl achieve in terms exp function on proven apex20k
- 2022-07-21 03:19:31下载
- 积分：1
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基于fpga和xinlinx ise的音乐播放器vhdl程序，希望对你有所帮助！...
基于fpga和xinlinx ise的音乐播放器vhdl程序，希望对你有所帮助！-and xinlinx ideally music player VHDL process, and I hope to help you!
- 2023-02-07 05:35:03下载
- 积分：1
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coe
自动计算fir滤波器系数的工具，不妨一试(Automatic calculation of filter coefficients fir tools, try)
- 2009-04-11 17:20:49下载
- 积分：1
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VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验...
VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验-VHDL by VGA interface standards, digital image signal conversion into a standard VGA format. Suitable for the pilot study
- 2022-05-08 02:59:08下载
- 积分：1
