登录
首页 » VHDL » Verilog

Verilog

于 2022-08-25 发布 文件大小:38.72 MB
0 56
下载积分: 2 下载次数: 1

代码说明:

Verilog-HDL程序设计实用教程收集,内容丰富,设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • verilog
    一些简单的Verilog代码,小例程,比如求平均值、七段数码管等等(Some simple Verilog code, small routines, such as averaging, seven digital tubes and so on)
    2016-12-12 10:02:20下载
    积分:1
  • 256M_sdram_OK
    改自特权同学verilog语言写sdram测试程序;支持256M内存(verilog sdram )
    2013-12-23 16:15:43下载
    积分:1
  • VGA count, PSW2 inverse control is counting? Reduced count, pop
    VGA计数,PSW2控制正逆计数,按下递减计数,弹起正向计数。利用VGA作为输出设备,显示计数值。-VGA count, PSW2 inverse control is counting? Reduced count, pop-up being counted. The use of VGA as the output equipment, revealed count.
    2022-04-17 09:49:34下载
    积分:1
  • yiweijicunq
    说明:  16位右移位寄存器 下面描述的是一个位宽为16位的右移位寄存器,实际具有环形移位的功能,是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时,输入信号的最低位移位到最高位,其余各位依次向右移动一位。(16-bit right shift register The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)
    2020-08-18 09:58:21下载
    积分:1
  • shumaguandongtai
    VHDL的动态扫描显示六个数码管,包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)
    2012-11-26 14:40:42下载
    积分:1
  • AD7991_7995_7999
    AD7991_7995_7999转换器说明(4-Channel, 12-/10-/8-Bit ADC with I2C-Compatible Interface in 8-Lead SOT-23)
    2013-05-15 20:14:11下载
    积分:1
  • imply logic
    说明:  由忆阻器机制设计蕴含逻辑,内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)
    2019-04-24 15:42:24下载
    积分:1
  • PID
    说明:  利用Verilog语言实现PID增量式控制,输出占空比(Using Verilog language to realize PID incremental control and output duty cycle)
    2020-04-24 10:06:59下载
    积分:1
  • goodProcessor.srcs
    说明:  处理器系统,处理器加上存储器,从存储器取出指令放入处理器执行(processor system, instructions stored in ROM, a counter generate address and the processor execute instructions.)
    2020-10-10 23:10:02下载
    积分:1
  • Verilog--Fourth-Edition
    FPGA开发必备工具书,适合初学者。语法、范例讲的都很详细,是一部不错的工具书。(Verilog hardware description language Fourth Edition)
    2015-09-30 12:34:50下载
    积分:1
  • 696518资源总数
  • 104297会员总数
  • 29今日下载