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APB 总线
APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
- 2017-08-22 16:04:06下载
- 积分：1
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turbo_encode
turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)
- 2014-03-29 15:09:58下载
- 积分：1
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UART的源（格版）
UART 源码 (lattice version)-UART source (lattice version)
- 2022-10-19 10:25:04下载
- 积分：1
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alu3
用verilog语言编写，一个8-bit ALU，可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)
- 2008-05-12 12:48:49下载
- 积分：1
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dingshi
定时器加数码管显示源码，以及test bench测试模块源码，经modelsim仿真结果正确(Timer plus digital display source code, and test bench test module source code, by modelsim simulation results are correct)
- 2013-07-27 10:34:41下载
- 积分：1
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乘法器的vhdl语言描述.本人调试已经通过
乘法器的vhdl语言描述.本人调试已经通过-Multiplier described in VHDL language. I have been through the debugging
- 2022-03-03 17:59:17下载
- 积分：1
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cam2
DE2-115 + D5M Camera to VGA PC
- 2020-07-09 19:48:55下载
- 积分：1
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ISE_uart
自己在ISE下用VHDL写的UART，简单，易懂(in ISE using VHDL was the UART, simple, understandable)
- 2021-03-08 21:59:28下载
- 积分：1
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irig_b
用来实现IRIG_B码的解码程序，在XILINX ISE上运行过没有问题，(Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,)
- 2021-04-06 14:49:03下载
- 积分：1
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VHDL-TESTBENCH
VHDL TESTBENCH书写规范，对学习FPGA的同学很有帮助，掌握仿真语言书写规范。(VHDL TESTBENCH description of the norms, the students learn FPGA helpful, master the language of simulation techniques)
- 2016-12-15 21:33:24下载
- 积分：1
