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FPGA设计全流程－软件综合使用、
FPGA设计全流程－软件综合使用、 -FPGA design of the whole process- the integrated use of software, FPGA design of the whole process- the integrated use of software,
- 2022-12-25 07:35:03下载
- 积分：1
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Using VHDL programming asynchronous FIFO procedure can be run by the debugger
使用VHDL编程的异步FIFO程序 经调试可运行-Using VHDL programming asynchronous FIFO procedure can be run by the debugger
- 2022-03-23 14:37:37下载
- 积分：1
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一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (mo...
一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
- 2022-08-21 18:15:23下载
- 积分：1
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利用扫描加记数程序实现百进制,适合VHDL的初学者使用.
利用扫描加记数程序实现百进制,适合VHDL的初学者使用.-increase in the use of scanning program in mind several hundred 229 and is suitable for beginners to use VHDL.
- 2022-03-21 06:59:03下载
- 积分：1
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liyuanlnx_IP_PLL
FPGA锁相环实验：
顶层文件加底层IP文件构成
top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)
- 2020-06-22 04:00:01下载
- 积分：1
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spi flash 控制器设计
基于FPGA的spi flash 控制器设计，详细的vhdl代码分析.......................................................................................................................................................................................................................
- 2022-07-04 03:02:41下载
- 积分：1
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使用CORDIC实现三角函数计算，使用VHDL语言实现
利用cordic实现三角函数的计算，用vhdl实现-use cordic achieve trigonometry calculations, using achieve vhdl
- 2022-01-20 22:30:42下载
- 积分：1
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rs_enc
Verilog code for RS-(255,239) encoder.
- 2021-04-06 16:19:02下载
- 积分：1
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src
Crossroad traffic lights with visualization in tcl/tk and verilog code
- 2010-07-22 03:43:55下载
- 积分：1
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weifen-program
基于FPGA微分程序代码及其电路驱动程序(Based on FPGA differential program
)
- 2011-12-19 12:17:59下载
- 积分：1
