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CLZ32
针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design
Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If
all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )
- 2021-03-31 19:39:08下载
- 积分：1
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taxi
利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)
- 2011-08-30 08:18:51下载
- 积分：1
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USB IPcoreIP核 包含文档(带说明)
USB IPcoreIP核 包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)
- 2022-02-18 17:02:37下载
- 积分：1
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final-delivery
Block LU decompostion of a matrix
- 2014-10-08 15:33:16下载
- 积分：1
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inc_pid
基于FPGA的增量式PID设计方法，Matlab、Simulink， Xilinx Block set(Incremental PID FPGA-based design methodology)
- 2014-11-03 04:16:19下载
- 积分：1
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一个8位CISC结构的精简CPU，2还提供了编译器
一个8位CISC结构的精简CPU，2还提供了编译器-an eight streamline the structure of the CISC CPU, the two also provided compiler
- 2022-02-28 11:37:41下载
- 积分：1
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fft in dspbuilder under VHDL source code and test incentives document matl ab mo...
fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
- 2022-03-14 15:52:36下载
- 积分：1
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八路AD采集adc128s022
FPGA AD采集八路数据，12位分辨率，小梅哥FPGA的开发程序，实测可用(FPGA AD collects eight path data, 12 bit resolution, and the development program of Mayo FPGA.)
- 2020-12-17 16:59:11下载
- 积分：1
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msttr是用vhdl语言开发的一个交通灯程序
msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures
- 2022-02-25 21:15:30下载
- 积分：1
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100例VHDL语言解释，北京理工大学毕业…
VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是51~94个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC publication, here is the 51 ~ 94 examples
- 2022-04-16 00:12:16下载
- 积分：1
