taxi

代码说明：

  利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)

文件列表：

EDA出租车计费系统
.................\db
.................\..\test.asm.qmsg,1715,2011-08-24
.................\..\test.cbx.xml,86,2011-08-24
.................\..\test.cmp.cdb,35180,2011-08-24
.................\..\test.cmp.hdb,8642,2011-08-24
.................\..\test.cmp.kpt,204,2011-08-24
.................\..\test.cmp.logdb,4,2011-08-24
.................\..\test.cmp.rdb,21891,2011-08-24
.................\..\test.cmp.tdb,25227,2011-08-24
.................\..\test.cmp0.ddb,39480,2011-08-24
.................\..\test.dbp,0,2011-08-24
.................\..\test.db_info,136,2011-08-24
.................\..\test.eco.cdb,141,2011-08-24
.................\..\test.fit.qmsg,45340,2011-08-24
.................\..\test.hier_info,4863,2011-08-24
.................\..\test.hif,559,2011-08-24
.................\..\test.map.cdb,9735,2011-08-24
.................\..\test.map.hdb,8154,2011-08-24
.................\..\test.map.logdb,4,2011-08-24
.................\..\test.map.qmsg,1668,2011-08-24
.................\..\test.pre_map.cdb,8701,2011-08-24
.................\..\test.pre_map.hdb,8377,2011-08-24
.................\..\test.psp,0,2011-08-24
.................\..\test.rtlv.hdb,8370,2011-08-24
.................\..\test.rtlv_sg.cdb,8651,2011-08-24
.................\..\test.rtlv_sg_swap.cdb,158,2011-08-24
.................\..\test.sgdiff.cdb,9469,2011-08-24
.................\..\test.sgdiff.hdb,9174,2011-08-24
.................\..\test.signalprobe.cdb,418,2011-08-24
.................\..\test.sim.hdb,2449,2011-08-24
.................\..\test.sim.qmsg,3558,2011-08-24
.................\..\test.sim.rdb,4974,2011-08-24
.................\..\test.sim_ori.vwf,32708,2011-08-24
.................\..\test.sld_design_entry.sci,134,2011-08-24
.................\..\test.sld_design_entry_dsc.sci,134,2011-08-24
.................\..\test.syn_hier_info,0,2011-08-24
.................\..\test.tan.qmsg,43837,2011-08-24
.................\..\wed.zsf,123,2011-08-24
.................\ntaix.bsf,3514,2011-08-24
.................\ntaix.v,1231,2011-08-24
.................\sel.bsf,5694,2011-08-24
.................\sel.v,1032,2011-08-24
.................\taxi.vwf,32711,2011-08-24
.................\test.asm.rpt,5705,2011-08-24
.................\test.bdf,19418,2011-08-24
.................\test.done,26,2011-08-24
.................\test.fit.rpt,99832,2011-08-24
.................\test.fit.smsg,411,2011-08-24
.................\test.fit.summary,402,2011-08-24
.................\test.flow.rpt,4128,2011-08-24
.................\test.map.rpt,19806,2011-08-24
.................\test.map.summary,311,2011-08-24
.................\test.pin,30322,2011-08-24
.................\test.qpf,901,2011-08-24
.................\test.qsf,1900,2011-08-24
.................\test.qws,1472,2011-08-24
.................\test.sim.rpt,35742,2011-08-24
.................\test.tan.rpt,78436,2011-08-24
.................\test.tan.summary,1682,2011-08-24