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CNA总线协议控制器Verilog
This CAN Controller was tested with the Bosch VHDL Reference Model and
passed all the tests. Because of the licensing issue it can not be
published on the Opencores web site.
The Can Controller was also implemented in real HW (12 boards
were constantly talking to each other).
The included test bench is not a real test bench and should be improved.
However a volunteer is needed for such a job. I can provide some help
but am not willing to write it by myself.
- 2022-05-26 04:35:56下载
- 积分：1
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HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分：1
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DS18B20
DS18B20温度传感器的基于FPGA的编程通信，使用VHDL语言(DS18B20 temperature sensor based FPGA programming communication with VHDL)
- 2012-07-16 19:10:29下载
- 积分：1
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VerilogHDL_advanced_digital_design_code_Ch4
Verilog HDL 高级数字设计源码 _chapter4(Advanced Digital Design Verilog HDL source _chapter4)
- 2007-11-27 10:10:43下载
- 积分：1
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fpga串口的接收程序
fpga串口的接收程序基于verilog语言拿走不用谢。(The receiving program of FPGA serial port is based on Verilog language.)
- 2020-06-18 03:20:02下载
- 积分：1
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shuzihongdianlu
数字钟电路的实现，可以24小时计时，可调整时间！(Digital clock circuit implementation, a 24-hour timer, adjustable time!)
- 2013-08-18 14:49:14下载
- 积分：1
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LDPC.DIFFERENT-RATE
LDPC码不同码率对比，1/2与1/3码率对比。码长512.迭代次数50次。(Comparison of different rate of the LDPC code, 1/2 compared with the 1/3 code rate. 512 yards long. 50 times the number of iterations.)
- 2012-11-22 10:49:22下载
- 积分：1
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6_42
An FPGA Implementation of a HoG-based Object Detection Processor
- 2016-04-07 23:42:05下载
- 积分：1
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Farrow
matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)
- 2021-03-28 22:29:11下载
- 积分：1
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AES（Rijndael）IP核的Verilog代码
应用背景16字节的块大小16字节的密钥大小单独的密码（加密）块单独的倒密码（解密）块注册密钥扩展模块verilog写的关键技术简单的AES（Rijndael）IP核。我曾试图平衡这一实施，并权衡规模和性能。目标是要能够以低成本Xilinx的Spartan系列FPGA还能够尽可能的快。正如一个可以从下面的实施结果来看，这个目标已经实现！不同的关键尺寸本标准其他实现（192 &；256位）和性能属性（如全流水线的超高速版）市售asics.ws。尽管没有官方的测试已经完成，我们认为这个核心是完全符合FIPS-197（PDF）。更多信息见核心文档；
- 2022-01-22 15:48:20下载
- 积分：1
