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one_2017_v2
说明: 一个编码解码系统,其中包含一个信号发生器(用查找表方式实现)、一个m序列生成器(用来编码和解码用)、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。(An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data.)
- 2021-03-15 18:24:40下载
- 积分:1
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FPGA I2C IP
应用背景i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the
implementation of custom I2C slave devices. The core provides a means to read and write
up to 256 8-byte registers. These registers can be connected to the users custom logic,
thus implementing a simple control and status interface.关键技术The core has up 256 registers that can be accessed via I2C. I2C write operations are used
to set the register address pointer, and write the register data. I2C reads are used to read
the register data. Successive data reads or writes result in data being read or written from
incremental register addresses. There is no limit on how much data can be read or written
in a single access, but the internal register address pointer will wrap round to 0 once it
reaches 255. Note that the address pointer is not initialized at reset, and the address
pointer must
- 2022-05-22 00:28:39下载
- 积分:1
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uart code dsdlab with my clock code
uart代码dsdlab与我的时钟代码.it是一个用于实现uart设计的verilog代码代码。这个是数字系统设计实验室的实践。
- 2022-09-14 16:00:03下载
- 积分:1
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用vhdl写实用96例子
用vhdl写实用96例子, 有RAM,PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)
- 2017-09-13 14:55:39下载
- 积分:1
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256M_sdram_OK
改自特权同学verilog语言写sdram测试程序;支持256M内存(verilog sdram )
- 2013-12-23 16:15:43下载
- 积分:1
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pj_gtx
说明: 利用高速口GTX进行快速的数据传输,包括接受和发送模块,用途广泛(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)
- 2019-03-25 21:40:10下载
- 积分:1
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电梯控制器
一个9层电梯的代码。每层电梯入口处,要求开关1,电梯内设有乘客到达的停止开关的水平。(没有下降的按钮,一楼九楼没有上行键)
- 2023-08-07 07:00:03下载
- 积分:1
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实现在屏幕上显示绿色和红色相间的水平条纹
实现在屏幕上显示绿色和红色相间的水平条纹。其中,vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)
- 2020-06-24 02:00:02下载
- 积分:1
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Taxi-automatic-billing
出租车自动计费系统的verilog程序代码(Taxi automated billing system verilog code)
- 2009-10-08 10:07:15下载
- 积分:1
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CPU
十一和通过vivado实现多周期cpu,各种作业再里面包含了(Realizing multi period CPU)
- 2020-12-29 10:19:00下载
- 积分:1