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verilog motor control
verilog motor control
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- 积分:1
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LDPC码的消息节点(Bitnode)消息更新过程的VHDL语言实现
LDPC码的消息节点(Bitnode)消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
- 2022-12-16 00:40:03下载
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串并转换程序,由串行输出转换为4位的并行输出
串并转换程序,由串行输出转换为4位的并行输出-String and the conversion process, from the serial output is converted to 4-bit parallel output
- 2022-04-12 06:17:43下载
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submodule
verilog 双模块算术平均值计算模块,子模块在时钟上升沿技术,高层模块根据当前计数值计算算数平均(verilog double module arithmetic mean calculation module, sub-module in the clock rising edge technology, high-level module is calculated based on arithmetic average of the current count)
- 2011-01-05 22:49:16下载
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FPGA based implementation of a SDR
FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
- 2022-12-18 09:05:03下载
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青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA,自己写的AVALON总线IP核,供大家参考...
青云开发的LCD模块LCM240128ZK3用于ALTERA的FPGA,自己写的AVALON总线IP核,供大家参考-err
- 2022-04-07 09:35:28下载
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PN-(2)
伪随机序列FPGA 通过仿真 M3000(Pseudo-random sequence M3000 FPGA simulation)
- 2011-06-09 13:40:00下载
- 积分:1
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422
串口收发,实现可调波特率的串口通信,verilog源码(Serial port and transceiver)
- 2021-04-07 15:19:01下载
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axi_master
自己写的 AXI master code(AXI master code)
- 2014-10-20 15:53:41下载
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01_基于ZYNQ的FPGA基础入门
说明: VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)
- 2020-06-17 12:00:01下载
- 积分:1