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loop
对锁相环路的仿真,二阶环的仿真与分析都可以通过这个文件来到完成(Simulation of PLL, second-order loop simulation and analysis can be completed by the adoption of the document came)
- 2008-12-17 23:00:35下载
- 积分:1
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gamefive
高精度小数除法器设计与实现。
在FPGA开发板上实现小数除法器,输入输出信号N_in [15:0], D_in[15:0],N_in[15:0]小于D_in,即被除数小于除数,输出商Q_out[15:0]中Q[15]一定为0,Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)
- 2017-01-01 17:32:25下载
- 积分:1
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基于fpga的自动售货机
用verilog状态机实现的自动售货机,是一次课程作业,参考了网上的例子进行了修改(Automatic vending machine implemented with Verilog state machine)
- 2018-06-25 22:18:06下载
- 积分:1
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CRC_restored
mpeg-2 crcr32计算的代码,采用verilog编写,验证通过(mpeg-2 crcr32 caculate)
- 2011-09-25 10:54:08下载
- 积分:1
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429NEW-03-15
429总线通过FPGA直接实现发送程序,通过Verilog实现(send 429 message by Verilog and FPGA )
- 2021-04-23 09:58:48下载
- 积分:1
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clock
本程序实现数字钟系统,有整点报时功能,可显示切换年月日,定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)
- 2015-04-19 22:07:02下载
- 积分:1
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512×8bid的FIFO 含工程文件,基于QUARTUs
512×8bid的FIFO 含工程文件,基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
- 2022-03-14 07:41:33下载
- 积分:1
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modelsim_ug
Mentor Graphics ModelSim User s Guide Software v6.3g
- 2010-04-18 13:30:25下载
- 积分:1
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gcounter1
数字钟vhdl实现,在线测试无误,具有闹钟,对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)
- 2013-10-19 22:06:16下载
- 积分:1
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Verilog
这是个关于verilog入门的文档,有同志对verilog感兴趣,可以下载此文档,以供参考。(This is a verilog entry on the document, there are comrades of the verilog interested, you can download this document for reference.)
- 2011-11-06 13:18:07下载
- 积分:1