-
CycloneII_NiosII_2C35_Rev02_DB_SCH
说明： nios开发板电路图CycloneII_NiosII_2C35_Rev02_DB_SCH.zip(nios development board circuit CycloneII_NiosII_2C35_Rev02_DB_SCH.zip)
- 2010-03-28 20:50:27下载
- 积分：1
-
ds180_7Series_Overview
对赛灵思7系列的三种型号的FPGA进行了综述(xilinx 7 productin overview)
- 2012-06-13 15:04:23下载
- 积分：1
-
SMBus
SMBus控制器的VHDL源码程序，适用于Quartus2，ISE等开发环境。(The SMBus controller VHDL source code procedures applicable to Quartus2 ISE development environment.)
- 2021-03-24 18:39:14下载
- 积分：1
-
本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有...
本源码为Nios II的开发示例,主要演示Nios II的I2C总线设计。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II I2C-bus design. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
- 2022-05-20 17:06:23下载
- 积分：1
-
firhalfband
利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图，回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)
- 2020-07-03 21:40:02下载
- 积分：1
-
half_band
半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)
- 2020-12-23 10:59:07下载
- 积分：1
-
bubblesort1024ram
说明： 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流(Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.)
- 2010-03-24 15:19:50下载
- 积分：1
-
该项目是用于执行4位arethmatic操作和逻辑操作…
The project is used to perform the operation of 4 bit arethmatic and logical operation. the projcet is implemented in spartan 3E
- 2022-03-21 15:49:24下载
- 积分：1
-
csbar(3) : X"E0000" to X"E01FF"
-- M68008 Address Decoder
-- Address decoder for the m68008
-- asbar must be 0 to enable any output
-- csbar(0) : X"00000" to X"01FFF"
-- csbar(1) : X"40000" to X"43FFF"
-- csbar(2) : X"08000" to X"0AFFF"
-- csbar(3) : X"E0000" to X"E01FF"
-- download from www.pld.com.cn & www.fpga.com.cn
--- M68008 Address Decoder-- Address decod er for the m68008-- 0 asbar must be to enable any o utput-- csbar (0) : X "00000" to X "01FFF"-- csbar (1) : X "40000" to X "43FFF"-- csbar (2) : X "08000" to X "0AFFF"-- csbar (3) : X "E0000" to X "E01FF"-- download from www.pld. com.cn
- 2022-02-26 21:53:57下载
- 积分：1
-
FIFO程序，适用FPGA仿真的代码，有一定的价值
FIFO程序，适用FPGA仿真的代码，有一定的价值-FIFO
- 2022-08-10 12:12:14下载
- 积分：1
