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BulkIn是FPGA向CY7C68013发送数据
BulkOut是FPGA从CY7C68013接收数据,可以用LED显示...
BulkIn是FPGA向CY7C68013发送数据
BulkOut是FPGA从CY7C68013接收数据,可以用LED显示
-BulkIn is the FPGA to the CY7C68013 is BulkOut send data CY7C68013 receive data from the FPGA, you can use LED display
- 2022-08-15 04:42:44下载
- 积分：1
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my_booth_mp
booth algotihm verilog design and test
- 2016-06-14 16:02:10下载
- 积分：1
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callback
This is code of UVM CALLBACK function.
- 2020-06-24 15:40:02下载
- 积分：1
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一路24位计数器,cpu可直接读写计数器的计数值.
一路24位计数器,cpu可直接读写计数器的计数值.-All the way 24-bit counters, cpu can be directly read and write the total value counters.
- 2022-06-18 10:47:22下载
- 积分：1
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数字钟的VHDL源程序，可以实现在学校、年级的壮举…
数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
- 2022-06-12 19:46:36下载
- 积分：1
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fpga_ofdm
这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用，大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)
- 2007-06-13 00:02:43下载
- 积分：1
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alter FPGA，包含sdram的nios系统开发实验完整工程文件
alter FPGA，包含sdram的nios系统开发实验完整工程文件-nios develop based nios IDE6.0，system involved an sdram
- 2022-02-13 18:25:41下载
- 积分：1
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zedboard
xilinx的zed板详细开发资料，对初学者和开发人员都有帮助(The Xilinx zed board detailed development information, helpful for beginners and developers)
- 2013-04-22 16:44:31下载
- 积分：1
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VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现...
VHDL电子抢答器的实现。有多个文件，主控件是用图行实现。其余各功能模块用VHDL实现-VHDL electronic Responder realized. A number of documents, the main controls are using maps the bank. The remaining modules using VHDL
- 2022-03-14 00:36:42下载
- 积分：1
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tanchishe-QuartusII
VGA显示FPGA实现的VHDL语言的贪吃蛇游戏设计
本设计分为6个模块主要是扫描模块 VGA现实和控制模块 游戏设计的模块 电源模块等
用QUARTUS2仿真运行(VGA display FPGA VHDL language to realize the Snake game design
The design is divided into six modules mainly scanning module VGA module power module and control module reality game design, etc.
Simulation run with QUARTUS2)
- 2020-11-06 10:09:50下载
- 积分：1
