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sixlift
一个数字电路设计：六层电梯自动运行的VHDL程序(a digital circuit:sixlift design)
- 2013-05-02 19:31:59下载
- 积分：1
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Noise-cancellation
this contain the source code for noise cancellation ,which can be used in c platform.
- 2012-10-21 23:32:37下载
- 积分：1
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lic_Xilinx_ISE_Vivado
这是Xilinx ISE 14.X以及vivado、vivado_hls的license，亲测可用(Xilinx ISE 14.x vivado, vivado_hls license, pro-test available)
- 2013-04-26 14:51:09下载
- 积分：1
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一种基于LUT的预失真方法。其中的一部分，有参考价值。
一种基于LUT的预失真方法。其中的一部分，有参考价值。-one method of DPD based on LUT
- 2022-06-30 17:35:36下载
- 积分：1
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这是一个FPGA sparttan 3E基础工程，
this a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.-this is a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.
- 2022-11-15 01:50:04下载
- 积分：1
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08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008
08EE06EDA 实验 4（VHDL 状态机设计_序列检测器）6/7/2008-design thesis requirement by vhdl
- 2022-03-29 09:41:25下载
- 积分：1
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bt1120
实现ITU-BT1120数字并行接口的编码和解码(decode and encode ITU-BT1120 parallel digital interface)
- 2021-01-12 12:08:48下载
- 积分：1
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simple code based on verilog
shifter , cla ,clg , ALU , PC
simple code based on verilog
shifter , cla ,clg , ALU , PC
- 2022-03-04 03:11:05下载
- 积分：1
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C4gx15_starter_qsys_pcie_gen1x1
PCIe demo sample code
- 2020-12-09 16:39:19下载
- 积分：1
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add16
designing of 16 bit adder using 4 bit adder using verilog code
- 2012-09-10 14:40:32下载
- 积分：1
