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QAM_verilog
基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 (FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.)
- 2021-02-22 18:29:41下载
- 积分：1
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本代码实现apb总线传输
本代码可实现apb总线的配置、传输等功能。代码已经经过仿真、验证，代码注释全面，简单易懂。本代码可实现apb总线的配置、传输等功能。代码已经经过仿真、验证，代码注释全面，简单易懂。本代码可实现apb总线的配置、传输等功能。代码已经经过仿真、验证，代码注释全面，简单易懂。
- 2022-05-05 19:48:12下载
- 积分：1
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基于Altera DE2的数字跑表设计
将100Hz，产生6计数器的100ms,1s,10s,1min,10min的时钟，有
- 2022-04-09 11:32:45下载
- 积分：1
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DATA_scramble
扰码器的verilog实现,参考802.11a相关标准(Scrambler in verilog implementation)
- 2009-12-20 16:44:15下载
- 积分：1
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业界标准的Verilog语法格式
verilog标准语法，还有很多的样例参考，学习的好资料。(Verilog standard grammar, there are many examples for reference, good learning materials.)
- 2020-06-15 22:50:02下载
- 积分：1
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UART 完整
复制去Google翻译翻译结果
- 2022-03-12 20:17:34下载
- 积分：1
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h_adder
ise13.2环境下VHDL编写的半加器器+仿真波形(ise13.2 environment half adder in VHDL simulation waveform control+)
- 2013-06-01 13:40:03下载
- 积分：1
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Read_SPI_ADC
This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.
- 2015-10-13 14:43:13下载
- 积分：1
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fpga
VHDL语言编程简单实例若干，适合于初学者(VHDL language programming simple example, suitable for beginners)
- 2013-01-22 14:44:00下载
- 积分：1
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16b20b_Encoder
16b20b encoder and decoder
- 2013-02-04 13:24:46下载
- 积分：1
