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sync-and-asyn_FIFO_verilog
同步与异步FIFO的verilog实现,包括源代码,testbench,测试以及综合通过,还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)
- 2021-03-07 14:19:29下载
- 积分:1
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Arty-Z7-20-hdmi-out-master
Arty Z7 20 HDMI output
- 2021-04-24 15:18:47下载
- 积分:1
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test-bench
如何编写测试文件,,test bench的编写方法和是列,,总结的非常好的东西(how to code test bench in verilog)
- 2012-03-31 08:38:24下载
- 积分:1
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static-timing-analyze
特权同学主讲的FPGA设计的时序约束专题(STA部分)(Speaker privileged classmates timing constraints for FPGA design topics (STA section))
- 2013-07-11 13:23:46下载
- 积分:1
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buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键...
buffer_display是4X4KEYPAD的输出显示模块。可以显示6个连续的按键-buffer_display is 4X4KEYPAD output module. It showed six consecutive Press
- 2022-12-12 05:35:03下载
- 积分:1
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irdecode
自己编写的红外解码子程序,但CPU资源占用较高,作教学示范用途。(prepared their infrared decoding routines, but higher occupancy CPU resources for teaching demonstration purposes.)
- 2006-11-05 13:51:28下载
- 积分:1
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vhdl_ders_1_temel_bilgiler
VHTL PROGRAMMING COURSE
- 2009-07-11 22:24:59下载
- 积分:1
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ARM-Verilog-HDL-IP-CORE
ARM处理器的IP核,用verilog编写的,对处理器和相关的CPU架构知识有很大帮助。(ARM processor IP core, written in verilog processor and CPU architecture knowledge.)
- 2020-09-21 10:27:52下载
- 积分:1
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proj-ASC
simple microprocessor that gives the greatest common divisor of 2 (4bit) numbers
- 2014-11-05 06:32:53下载
- 积分:1
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multiplier
参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )
- 2011-12-08 15:14:04下载
- 积分:1