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74ls138-integral-4-wire-encoder-16
74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)
- 2011-09-20 19:00:59下载
- 积分:1
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cnt60
60进制计数器,(由一六进制和十进制连线组成)(60 binary counter (hexadecimal and decimal by a connection form))
- 2011-11-29 10:48:37下载
- 积分:1
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VHDL_biss
FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)
- 2021-03-15 19:19:22下载
- 积分:1
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2D4N_com
2维4节点的UEL单元,嵌入UMAT,采用j2 mises屈服准则(2d4nodes uel elements, with umat codes, and j2 mises flow rule)
- 2014-06-04 20:43:21下载
- 积分:1
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cn1
在MATLAB的SIMULINK中,用DSPBUILDER实现计数功能,控制LED指示灯.(In MATLAB SIMULINK, DSPBUILDER is used to realize counting function and control LED indicator lamp.)
- 2018-08-16 15:35:47下载
- 积分:1
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data_swith
verilog 代码实现串并转换,有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分:1
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arinc429转232接口协议
资源描述arinc429与232接口协议之间的数据传输代码
- 2022-06-28 17:56:18下载
- 积分:1
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pll_carrier_syn
本程序是锁相环的仿真程序,具有接收端载波同步的功能。注释详尽,程序规范。发端的调制方式有单载波调制,BPSK调制,QPSK调制可供选择。程序中有星座图,锁相环的频差、相差图,以及解调后的基带波形。(This program is a phase-locked loop simulation program, the with carrier synchronization receiving end function. Notes detailed program specifications. The originator of the modulation scheme to choose a single carrier modulation, BPSK modulation, QPSK modulation. Program constellation diagram, the PLL frequency difference, a difference of FIG, and the demodulated baseband waveform.)
- 2013-04-11 09:18:49下载
- 积分:1
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FFT_FPGA_Verilog-master
xilinx ise开发环境中fft IP核调用,仿真(Xilinx ise development environment FFT IP core call, simulation)
- 2018-07-08 23:28:46下载
- 积分:1
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曼彻斯特编码和解码
它包含了曼彻斯特编码和解码的Verilog文件。它解释了曼彻斯特编码方案和解码方案的基本原则1553总线结构。它给人的主意,还写Verilog代码
- 2022-04-16 20:33:22下载
- 积分:1