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sch_tbf
Token Bucket Filter queue.
- 2013-05-06 11:34:24下载
- 积分:1
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华为 Verilog基本电路设计指导书
说明: 华为 Verilog基本电路设计指导书--本文列举了大量的基本电路的Verilog HDL 代码,使初学者能够迅速熟悉基本的HDL 建模;同时也列举了一些常用电路的代码(Huawei Verilog basic circuit design instruction)
- 2020-07-04 11:00:01下载
- 积分:1
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FPGA DDS
说明: 使用DE2实现DDS,步骤简单,配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)
- 2020-06-23 10:00:01下载
- 积分:1
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sata3.0协议及FPGA各模块实现
说明: sata3.0协议及FPGA各模块实现,有代码及文档说明。(Sata3.0 protocol and FPGA module implementation, with code and documentation.)
- 2020-02-13 01:02:31下载
- 积分:1
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bingchuan
说明: 简单的vhdl的四位并串转换程序,可以实现数据的并串转换(Simple vhdl string of four and the conversion process, can convert the data and the string)
- 2011-04-02 12:16:35下载
- 积分:1
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VHDL.Programming
这是这本书的第四个版本,现在这个版本不仅提供了VHDL语言的覆盖面,但设计方法的信息,以及。此版本将指导读者通过创建一个VHDL设计的过程中,模拟设计,综合设计,放置和布线设计,使用的重要模拟验证的最终结果,新的技术,称为全速调试,提供了极其快速设计验证。在这个版本的设计,例如已被更新(This is the fourth version of the book and this version now not only provides VHDL language coverage but design methodology information as well. This version will guide the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result, and a new technique called At-Speed debugging that provides extremely fast design verification. The design example in this version has been updated to reflect.)
- 2012-04-08 19:36:36下载
- 积分:1
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rs-decoder-make-byvhdl
- RS码是Reed-Solomon 码(理德-所罗门码)的简称,它是一类非二进制BCH码,在RS码中,输入信号分成k·m比特一组,每组包括k个符号,每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)
- 2021-04-28 15:58:44下载
- 积分:1
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VHDL的寄存器读写参考,可自己根据要求重新修改,本示范只做参考用...
VHDL的寄存器读写参考,可自己根据要求重新修改,本示范只做参考用-Register read and write VHDL reference to their request to amend in accordance with, the reference model only
- 2022-09-23 06:45:03下载
- 积分:1
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Project7_5
说明: 基于fpga状态机的交通灯设计,亮灯时间自己修改,程序简单易懂。(Traffic light design based on FPGA state machine, light time self-modifying, the program is simple and easy to understand.)
- 2020-06-18 04:00:01下载
- 积分:1
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blocking
基于verilog语言的数据选择器,包括数据选择器的测试模块
(verilog language based on the data selector, including data selection for the test module)
- 2007-03-22 09:05:10下载
- 积分:1