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verilog-lfsr-master
说明： Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR next state computation. Includes full MyHDL testbench.
- 2020-06-24 21:40:01下载
- 积分：1
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BNN-PYNQ-master
在PYNQ-Z1上搭建二值神经网络(BNN)(Building two value neural network (BNN) on PYNQ-Z1)
- 2018-01-15 11:34:33下载
- 积分：1
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FPGA 出租计费器
本代码绝对真实可靠，原用于长沙理工大学EDA课程设计之出租车计费器。本代码在要求的基础上添加显示时速和报警功能。希望此代码对有此需求的同学有所帮助！
- 2022-01-25 20:43:32下载
- 积分：1
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This code for countor . it is design in verilog HDL.
This code for countor . it is design in verilog HDL.
- 2022-07-27 18:33:04下载
- 积分：1
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chenxu
电子时钟，可以显示四位，两位显示分钟，两位显示秒，可以用按键控制清零，以及加减数(Electronic clock, you can display four bit, two bit display minutes, the second display seconds, can be used to control the key to clear, and the addition of subtraction)
- 2017-04-22 21:29:14下载
- 积分：1
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波形发生器，带TESTBENCH，
多平台
波形发生器，带TESTBENCH，
多平台
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
-waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
- 2023-05-18 16:15:03下载
- 积分：1
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PID
用Verilog HDL编写的PID程序代码，成功调试，运行良好。(The source code of PID in Verilog HDL.Simulation was successful.)
- 2012-03-09 11:18:17下载
- 积分：1
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VHDL经典教程,下了不会后悔
VHDL经典教程,下了不会后悔-VHDL Tutorial classic, the next will not regret it
- 2022-01-25 20:37:44下载
- 积分：1
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具有多种功能的电子钟：闹钟、定时和修改…
具有多种功能的电子钟：闹钟，报时和修改，定时闹钟，报时时间，带闹钟，报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
- 2022-03-12 23:49:24下载
- 积分：1
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Roy dsd
说明： basic verilog code on siso, piso, sipo
- 2020-06-25 18:40:01下载
- 积分：1
