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BCD_to_7_seg_decoder
BCD to 7 segments display decoder
- 2015-06-15 22:36:01下载
- 积分:1
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verilog-SPI-core
用VerilogHDL写的spi 核的例子(A simple example of SPI core using Verilog HDL)
- 2011-08-31 20:37:07下载
- 积分:1
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XUAN-ZHUAN-led
旋转LED 实现自适应转速 字幕滚动 对接的程序(Rotating LED Adaptive Speed subtitles scroll docking program)
- 2013-02-06 16:17:56下载
- 积分:1
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OFDM_Verilog实现
使用Verilog语法编写OFDM系统,可借鉴学习,包括发射和接收两部分,发射部分有时钟,映射,交织,加CP、长短训练符号等模块,接收部分有频偏估计,解交织,解映射,维特比译码等模块
- 2023-06-03 16:50:04下载
- 积分:1
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VHDL
用VHDL语言实现一Mealy型时序电路,并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)
- 2014-03-20 14:44:28下载
- 积分:1
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flash_programming
主控cc2530通过debug接口对目标cc2530进行程序烧写,使用DMA进行数据传输,已调试通过。(Master cc2530 through the debug interface for writing the program to target cc2530, using the DMA data transfer, has been work successful.)
- 2011-08-21 23:42:58下载
- 积分:1
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DPD_project
预失真算法中,包络解波部分的verilog代码,有部分错误(envelope calculation of DPD algorithm ,verilong HDL language)
- 2014-04-26 15:45:21下载
- 积分:1
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NAND_flash_verilog_vhdl
很好的NAND Flash 硬件驱动语言,支持VHDL和verilog 语言方便移植,如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference
This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host
end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address
bus, data bus, error status signal, control and handshake signals for the user......)
- 2021-03-08 22:59:28下载
- 积分:1
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AD_R
AD7685芯片采集程序,可以自行设置采样率,经检验可用。(The AD7685 chip collection procedures, available.)
- 2020-12-20 14:19:08下载
- 积分:1
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lcd-ip-core
LCD 驱动的IPCORE,可用于alteraFPGA(LCD driver IPCORE, can be used to alteraFPGA)
- 2011-02-15 11:34:38下载
- 积分:1