NAND_flash_verilog_vhdl

代码说明：

  很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address bus, data bus, error status signal, control and handshake signals for the user......)

文件列表：

NAND_flash_verilog_vhdl
.......................\doc
.......................\...\rd1055.pdf,628647,2010-10-12
.......................\...\rd1055_readme.txt,13530,2010-10-13
.......................\project
.......................\.......\nand_flash_cntl.lpf,91,2009-06-30
.......................\.......\nfcm_tb_vhd.udo_example,338,2010-10-13
.......................\simulation
.......................\..........\verilog
.......................\..........\.......\rtl_verilog.do,101,2010-10-13
.......................\..........\.......\timing_verilog.do,228,2010-10-13
.......................\..........\vhdl
.......................\..........\....\rtl_vhdl.do,103,2010-10-13
.......................\..........\....\timing_vhdl.do,234,2010-10-13
.......................\source
.......................\......\verilog
.......................\......\.......\ACounter.v,3023,2010-01-19
.......................\......\.......\ErrLoc.v,2766,2010-01-19
.......................\......\.......\H_gen.v,2863,2010-01-19
.......................\......\.......\ipexpress
.......................\......\.......\.........\xo
.......................\......\.......\.........\..\ebr_buffer.lpc,891,2009-05-08
.......................\......\.......\.........\..\ebr_buffer.v,8961,2009-05-08
.......................\......\.......\.........\xo2
.......................\......\.......\.........\...\ebr_buffer.lpc,797,2010-10-12
.......................\......\.......\.........\...\ebr_buffer.v,14227,2010-10-12
.......................\......\.......\.........\xp2
.......................\......\.......\.........\...\ebr_buffer.lpc,892,2009-10-28
.......................\......\.......\.........\...\ebr_buffer.v,5134,2009-10-28
.......................\......\.......\MFSM.v,20548,2010-01-19
.......................\......\.......\nfcm_top.v,9454,2010-01-19
.......................\......\.......\nfcm_top.vhd,13418,2010-01-19
.......................\......\.......\TFSM.v,8246,2010-01-19
.......................\......\vhdl
.......................\......\....\ACounter.vhd,3113,2010-01-19
.......................\......\....\ErrLoc.vhd,3284,2010-01-19
.......................\......\....\H_gen.vhd,3278,2010-01-19
.......................\......\....\ipexpress
.......................\......\....\.........\xo
.......................\......\....\.........\..\ebr_buffer.lpc,884,2010-01-11
.......................\......\....\.........\..\ebr_buffer.vhd,12800,2010-01-11
.......................\......\....\.........\xo2
.......................\......\....\.........\...\ebr_buffer.lpc,790,2010-10-12
.......................\......\....\.........\...\ebr_buffer.vhd,16780,2010-10-12
.......................\......\....\.........\xp2
.......................\......\....\.........\...\ebr_buffer.lpc,885,2010-01-15
.......................\......\....\.........\...\ebr_buffer.vhd,9529,2010-01-15
.......................\......\....\MFSM.vhd,28539,2010-01-19
.......................\......\....\nfcm_top.vhd,13418,2009-06-25
.......................\......\....\TFSM.vhd,9789,2010-01-19
.......................\testbench
.......................\.........\verilog
.......................\.........\.......\flash_interface.v,8160,2009-06-30
.......................\.........\.......\nfcm_tb.v,9248,2009-12-16
.......................\.........\vhdl
.......................\.........\....\flash_interface.vhd,12643,2010-01-19
.......................\.........\....\nfcm_tb.vhd,11693,2010-01-19
RD1055
......\doc
......\...\rd1055.pdf,628647,2010-10-12
......\...\rd1055_readme.txt,13530,2010-10-13
......\project
......\.......\nand_flash_cntl.lpf,91,2009-06-30
......\.......\nfcm_tb_vhd.udo_example,338,2010-10-13
......\simulation
......\..........\verilog
......\..........\.......\rtl_verilog.do,101,2010-10-13
......\..........\.......\timing_verilog.do,228,2010-10-13
......\..........\vhdl
......\..........\....\rtl_vhdl.do,103,2010-10-13
......\..........\....\timing_vhdl.do,234,2010-10-13
......\source
......\......\verilog
......\......\.......\ACounter.v,3023,2010-01-19
......\......\.......\ErrLoc.v,2766,2010-01-19
......\......\.......\H_gen.v,2863,2010-01-19
......\......\.......\ipexpress
......\......\.......\.........\xo
......\......\.......\.........\..\ebr_buffer.lpc,891,2009-05-08
......\......\.......\.........\..\ebr_buffer.v,8961,2009-05-08
......\......\.......\.........\xo2
......\......\.......\.........\...\ebr_buffer.lpc,797,2010-10-12
......\......\.......\.........\...\ebr_buffer.v,14227,2010-10-12
......\......\.......\.........\xp2
......\......\.......\.........\...\ebr_buffer.lpc,892,2009-10-28
......\......\.......\.........\...\ebr_buffer.v,5134,2009-10-28
......\......\.......\MFSM.v,20548,2010-01-19
......\......\.......\nfcm_top.v,9454,2010-01-19
......\......\.......\nfcm_top.vhd,13418,2010-01-19
......\......\.......\TFSM.v,8246,2010-01-19
......\......\vhdl
......\......\....\ACounter.vhd,3113,2010-01-19
......\......\....\ErrLoc.vhd,3284,2010-01-19
......\......\....\H_gen.vhd,3278,2010-01-19
......\......\....\ipexpress
......\......\....\.........\xo
......\......\....\.........\..\ebr_buffer.lpc,884,2010-01-11
......\......\....\.........\..\ebr_buffer.vhd,12800,2010-01-11
......\......\....\.........\xo2
......\......\....\.........\...\ebr_buffer.lpc,790,2010-10-12