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429recive
实现FPGA接收429板卡发送的信号,并根据数据最后两位点亮相应的LED。(FPGA to achieve the 429 board to receive the signal sent, and according to the data of the last two of the corresponding LED.)
- 2015-11-26 11:18:19下载
- 积分:1
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带FIFO的ov7670 FPGA应用程序,经测试可用
这是用Verilog编写的OV7670摄像头驱动代码,带FIFO,经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)
- 2021-04-08 21:19:00下载
- 积分:1
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adder2
此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ,特别是模为 60 的 BCD码加法计数器,这是我目前发现的最优源代码,应用于解码器领域。(This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field.)
- 2010-10-30 15:14:06下载
- 积分:1
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msttr是用vhdl语言开发的一个交通灯程序
msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures
- 2022-02-25 21:15:30下载
- 积分:1
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verilog
一些简单的Verilog代码,小例程,比如求平均值、七段数码管等等(Some simple Verilog code, small routines, such as averaging, seven digital tubes and so on)
- 2016-12-12 10:02:20下载
- 积分:1
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JSFP
奇数分频-此程序对输入频率sysclk有奇数(X)分频的功能(Odd frequency- this program has an odd number of input frequency sysclk (X) frequency function)
- 2011-08-01 12:37:42下载
- 积分:1
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FIFO
fifo程序代码,程序编写,测试仿真图形,方便,比较实用(fifo code, programming, testing, simulation graphics, convenient and more practical)
- 2016-03-16 10:06:12下载
- 积分:1
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mike11xns
mike11河道断面处理软件,将断面格式写成11要求的格式(MIKE11 river section processing software, the section format 11 format
)
- 2021-04-06 17:29:02下载
- 积分:1
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VGA_FPGA
基于FPGA的VGA控制器,可在屏幕显示彩色条纹(A vga controller based on FPGA)
- 2014-08-15 21:35:07下载
- 积分:1
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io_uart
verilog设计的32位IO口扫描后通过串口发送到计算机(Verilog design of 32 bit IO export after scanning through the serial port to the computer)
- 2012-12-27 00:05:01下载
- 积分:1