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wcdma_reciever
本代码仿真了WCDMA小区搜索。cell_search_cpich scramble wcdmasource(This code emulation WCDMA cell search. cell_search_cpich scramble wcdmasource)
- 2020-11-24 16:39:34下载
- 积分：1
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QAM_verilog
基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 (FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.)
- 2021-02-22 18:29:41下载
- 积分：1
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FPGA-powe-analysis-tool-EPE
FPGA功耗分析工具EPE用于分析FPGA系统的功耗(FPGA power analysis tools EPE is used to analyze the power consumption of the FPGA system)
- 2012-11-19 17:08:00下载
- 积分：1
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Flash-Memory-RAM
周立功Fusion StartKit，fpga开发板的实验例程，Flash Memory初始化RAM实验(ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments)
- 2013-03-07 20:36:48下载
- 积分：1
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sobel
这是本人自己编写的可用于256*256大小的图像进行sobel边缘检测的vhd文件，可在QuartusII或MaxplisII下综合和仿真，并在FPGA上测试过。可以进行修改支持其他大小图像的sobel边缘检测，同时还可以实现其它的图像模块化处理算法，例如高斯滤波，平滑等。(this is my own preparation for the 256* 256 size of the image segmentation Edge Detection vhd document in the next QuartusII or MaxplisII integrated and simulation, and the FPGA tested. Can be adapted to support other size image segmentation edge detection, It can also achieve other modular image processing algorithms, such as Gaussian filtering, smoothing and so on.)
- 2020-07-09 21:08:55下载
- 积分：1
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scia_loopback_interrupts
TI F28027 SCI 源码，中断，FIFO，LoopBack使能(TI F28027 SCI source code, interrupt, FIFO and Loopback enalbe)
- 2020-11-18 15:29:40下载
- 积分：1
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shumaguandongtai
VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)
- 2012-11-26 14:40:42下载
- 积分：1
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双电梯控制器
说明： 使用verilog实现的双电梯控制器，1-9层，仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)
- 2020-06-17 11:44:27下载
- 积分：1
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原创verilog_16bit_risc_cpu，带相关PPT和testbench
原创verilog_16bit_risc_cpu，带相关PPT和testbench尚未进行冲突处理，代码还比较简单，方便新人学习，毕竟处理冲突后代码将会复杂很多。 继续关注我吧！ 等我做好优化和冲突处理后，还会放出来，现在已经想好思路了，就差通宵敲代码和调试了。 给我动力，我就可以翱翔蓝天！
- 2022-01-26 02:40:38下载
- 积分：1
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shuzishizhong
这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)
- 2013-12-10 22:21:55下载
- 积分：1
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