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VHDL-ELEVATOR-CONTORLLER-DESIGN
VHDL电梯控制器程序设计与仿真，内含原理图和VHDL源码，有助于学习VHFL(VHDL u7535 u68AF u63A7 u5236 u5668 u7A0B u5E8F u8BBE u8BA1 u4E0E u4EFF u771F)
- 2017-05-06 15:35:16下载
- 积分：1
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ALTERA_FPGA_SDRAM
使用ALTERA的FPGA控制SDRAM的verilog程序(Use ALTERA s FPGA to control SDRAM s verilog program)
- 2017-03-30 00:31:53下载
- 积分：1
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FP代码是用来实现aritjmetics
fp codes is used to realize the aritjmetics
- 2022-03-26 07:19:34下载
- 积分：1
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emifa_ram
FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序(FPGA and DSP EMIF communication)
- 2020-12-01 15:49:26下载
- 积分：1
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a lot of examples and test code, useful for beginners, it is easy to get started
有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started
- 2022-02-02 14:25:45下载
- 积分：1
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这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！...
这是“状态机设计（讲稿）”，希望对正在学VHDL的同学有帮助，谢谢！-This is the "state machine design (the script)", and I hope to learn VHDL is there to help the students, thank you!
- 2022-11-16 16:25:03下载
- 积分：1
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24小时计时时钟
实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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my_test_rw_pack9
基于Verilog HDL的SDRAM控制器。
实验条件：
工具：Quartus II 6.0 ,SignalTap II
FPGA：Altera Cyclone EP1C12Q240C8N
SDRAM：HY57V283220T-6(SDRAM controller based on Verilog HDL.
Experimental conditions:
Tools: Quartus II 6.0, SignalTap II
FPGA: Altera Cyclone EP1C12Q240C8N
SDRAM: HY57V283220T-6)
- 2013-01-31 11:13:26下载
- 积分：1
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单片机的4 am2901完整的VHDL程序，am2901
4位MCU AM2901的完整VHDL程序，AM2901为主程序，其他为实体库-4 MCU AM2901 complete VHDL program, AM2901-based procedures, other entities, the Treasury
- 2022-12-05 05:15:03下载
- 积分：1
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i2c_peri_demo_revC1
说明： I2C 从设备通讯应用示范程序，用于I2C设计验证(I2C slave communication application demo program, used to for I2C design verification )
- 2010-03-18 01:24:52下载
- 积分：1
