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verilog
说明: i2c module,有i2c主机和从机模块(i2c module verilog VHDL base on i2c protocol)
- 2020-10-26 08:27:29下载
- 积分:1
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SinglePeriodCPU
说明: verilog语言书写,单周期CPU源码(single period CPU)
- 2020-11-25 11:59:32下载
- 积分:1
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vhdl
code for fft non synthesisable in xilinx ise
- 2013-09-30 13:16:13下载
- 积分:1
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verilogdct
dct实现verilog hdl的数字图像处理,源代码(dct achieve verilog hdl digital image processing, source code)
- 2020-12-02 17:49:26下载
- 积分:1
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采用VHDL编写的一个简单的UART
采用VHDL编写的一个简单的UART-using VHDL prepared a simple UART
- 2022-03-05 06:29:41下载
- 积分:1
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This tutorial presents some basic concepts that can be helpful in debugging of a...
This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.
- 2022-08-19 12:45:10下载
- 积分:1
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VHDL实现led灯的动态扫描,主要对CLK进行分频
VHDL实现led灯的动态扫描,主要对CLK进行分频-VHDL realization led lamp dynamic scan, the main points of the CLK to the frequency
- 2023-03-21 08:35:04下载
- 积分:1
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chengxu
数字时钟,可以实现(1) 显示日期功能(年、月、日、时、分、秒以及)
(2) 可通过按键切换年、月、日及时、分、秒的显示状态
(3) 可随时调校年、月、日或时、分、秒
(4) 可每次增减一进行时间调节
(5) 可动态完整显示年份,实现真正的万年历显示
(6) 可显示温度
(Digital clock, can be achieved (1) the date function (year, month, day, hour, minute, seconds as well) (2) through the key switch the year, month, day in a timely manner, minute, second display state (3) at any time adjust the year, month, day or time, minutes, seconds (4) can be added or deleted, a time adjustment (5) can be dynamically complete display Year, the real calendar display (6) to display temperature)
- 2012-10-15 00:25:33下载
- 积分:1
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usb_test
Cypress USB 的主从FPGA 控制实现代码(USB controller)
- 2012-10-09 10:39:52下载
- 积分:1
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采用systemc语言设计了一个状态机,主要包括两个进程,仿真结果表明状态机可以正常工作...
采用systemc语言设计了一个状态机,主要包括两个进程,仿真结果表明状态机可以正常工作-Systemc language designed using a state machine, mainly consists of two processes, the simulation results show that the state machine can work properly
- 2022-03-17 09:47:30下载
- 积分:1