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666基于FPGA的MVB2类设备控制器设计_幸柒荣
本文首先对多功能车辆总线的基本原理进行了简要的概述，接着对其实时协议进行了分析，然后对 MVB2 类设备控制器的功能及其功能模块的划分设计进行了详细的分析；最后对各功能模块进行了编程实现，并给出了仿真验证波形。(Firstly, the basic principle of the multifunction vehicle bus are briefly outlined, then analyze the real time protocol, then carried out a detailed analysis of the classification of the design function and the function module of the MVB2 device controller; finally, the function of each module of the program, and gives the simulation waveforms.)
- 2017-10-24 10:57:41下载
- 积分：1
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ram32b
VHDL code for 32 byte RAM
- 2009-06-04 19:50:35下载
- 积分：1
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Serial_Adder
注意：是verilog语言写的
一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)
- 2020-10-30 20:09:55下载
- 积分：1
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clock_FPGA_verilog
简易电子钟的设计（verilog HDL）(Simple design of the electronic clock (verilog HDL))
- 2012-11-03 10:35:49下载
- 积分：1
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multiplay
连乘,乘法可以用简单的for循环，我这里用的是移位寄存器来做，而且是用来两个移位寄存器(this is a tool that function is multiplay,it use a special way to do multiplay .it will teach you the how to use labview )
- 2015-02-04 20:44:16下载
- 积分：1
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bldc_motor_control_design_example
无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA( actel VERILOG BLDC control of the use of actel FPGA)
- 2020-10-29 09:19:57下载
- 积分：1
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ytupn
Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.
- 2017-09-02 18:07:13下载
- 积分：1
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Nios_II_uCOS
本源码为Nios II的开发示例,主要演示基于Nios II的uCOS的移植。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。(The source code for the Nios II development of examples, mainly based on the Nios II shows the uCOS transplant. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.)
- 2009-12-18 14:08:40下载
- 积分：1
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ads7809
ADS7809是Burr-Brown公司推出的高精度AD采集芯片。它采用5V单电源供电,内含16位
逐次逼近寄存器,采样精度高,功耗小。
用Verilog实现其配置(ADS7809 is a Burr-Brown Introduces High Precision AD capture chip. It uses a single 5V supply, with 16-bit successive approximation register, sampling and high precision, low power consumption. To achieve its configuration with the Verilog)
- 2021-04-05 17:09:03下载
- 积分：1
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Xilinx-Timing
Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)
- 2013-05-17 09:31:26下载
- 积分：1
