网站首页

all passed, I was carefully designed, fully meet the requirements of beginners....

于 2022-05-05 发布文件大小:1.24 kB

 0  38

下载积分: 2 下载次数: 1

我要下载

代码说明：

全部通过，是我的精心设计，完全满足初学者的要求。0-99自动记数-all passed, I was carefully designed, fully meet the requirements of beginners. 0-99 automatic counting

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

uart
用veriolg 语言编写的串口通讯程序，通过FPGA控制串口的通讯。(a veriog program completed on FPGA to contrlo a uart to communicaton with a computer )

2010-08-16 10:41:03下载

积分：1
crc_verilog_xilinx
各类CRC效验码有CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8(CONTAIN CRC8-8 CRC16-8 CRC32-8 CRC12-4 CRC-CCIT-8 )

2021-03-10 22:59:26下载

积分：1
jtag
verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

2021-04-27 14:38:44下载

积分：1
USB 1.1 IP
USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code

2022-05-24 18:47:17下载

积分：1
这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化...
这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences

2022-03-23 10:36:34下载

积分：1
jisuanqishijianxianshi
基于FPGA编写一个时间显示，计数功能，年月显示的程序，(FPGA-based preparation of a time display, counting, years show program,)

2011-08-30 16:00:48下载

积分：1
Verilog HDL实现的I2C Slave模拟
Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave

2022-11-26 13:05:03下载

积分：1
FSK
2FSK的matlab仿真，叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)

2021-04-13 02:58:56下载

积分：1
MTKhardwaretraing
MTK平台硬件培训MTK平台硬件培训MTK平台 GSM双频手机接收信号处理流程MTK平台 GSM双频手机接收信号处理流程 (MTK platform hardware training platform hardware training MTK MTK GSM dual-band mobile phone platform to receive the signal processing)

2010-08-05 00:12:33下载

积分：1
cpld/fpga Integral comb filter (CIC) design
cpld/fpga积分梳状滤波器(CIC)设计-cpld/fpga Integral comb filter (CIC) design

2022-07-08 17:49:24下载

积分：1

696518资源总数
104297会员总数
29今日下载

all passed, I was carefully designed, fully meet the requirements of beginners....

0 个回复

热门标签

热门下载