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FPGA数码管显示秒表实验
说明: FPGA数码管显示秒表实验
三种方法实现:
方法一: 对秒计数,得到(秒显示)0~9,
对(秒显示)计数,得到(分秒显示)0~5,
对(分秒显示)计数,得到(分钟显示)0~5,
注意进位时机
方法二: 对秒计数,得到(秒显示)0~9
对秒计数,得到(分秒显示)0~5
对秒计数,得到(分钟显示)0~5
方法三:
只对秒计数,分别取模
%60得到分钟显示 ************************
余数%10得到分秒显示 (据说)取模运算占资源!!!!(也能接受?好像...)
再剩下的余数为秒显示 ************************(Experiment of Digital Tube Display Stopwatch Based on FPGA
Three ways to achieve)
- 2020-06-22 04:40:02下载
- 积分:1
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FPGA I2C IP
应用背景i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the
implementation of custom I2C slave devices. The core provides a means to read and write
up to 256 8-byte registers. These registers can be connected to the users custom logic,
thus implementing a simple control and status interface.关键技术The core has up 256 registers that can be accessed via I2C. I2C write operations are used
to set the register address pointer, and write the register data. I2C reads are used to read
the register data. Successive data reads or writes result in data being read or written from
incremental register addresses. There is no limit on how much data can be read or written
in a single access, but the internal register address pointer will wrap round to 0 once it
reaches 255. Note that the address pointer is not initialized at reset, and the address
pointer must
- 2022-05-22 00:28:39下载
- 积分:1
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h.264解码器Verilog
本代码为h.264解码器的Verilog代码,在本压缩包中包含了全部Verilog代码,亲测成功,可以使用。
- 2023-07-28 17:35:03下载
- 积分:1
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e1framer
E1 deframmer and Frammer.
- 2013-02-25 19:43:35下载
- 积分:1
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qpsk_demod_use_FPGA
根据软件无线电的思想,提出了一种新颖的数字信号处理算法,对QPSK信号的相位进行数字化处理,从而实现对QPSK信号的解调.该算法允许收发两端载波存在频差,用数字锁相实现收发端载波的同步,在频偏较大的情况下,估算频偏的大小,自适应设置环路的带宽,实现较短的捕获时间和较好的信噪性能。整个设计基于XILINX公司的ISE开发平台,并用Virtex-II系列FPGA实现。用FPGA实现调制解调器具有体积小、功耗低、集成度高、可软件升级、扰干扰能力强的特点,符合未来通信技术发展的方向。(According to the idea of software radio, a novel digital signal processing algorithm, the phase of QPSK digital signal processing, enabling the demodulation of QPSK signals. This algorithm allows the sending and receiving ends of the carrier frequency difference exists, using digital phase-locked to achieve synchronization of sending and receiving end of the carrier, in the case of large frequency offset, frequency offset estimation of the size, adaptive set the loop bandwidth to achieve shorter acquisition time and better noise performance. The whole design is based on the company XILINX ISE development platform, and Virtex-II series with the FPGA. FPGA realization of a modem with a small size, low power consumption, high integration, software upgrades available, the characteristics of strong interference interference, in line with the future direction of ICT development.)
- 2010-12-06 10:52:36下载
- 积分:1
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SPI verilog 源代码
串行外设接口或 SPI 总线是一个同步串行数据链接,一个事实上的标准,由摩托罗拉命名,在全双工模式下运行
。它用于短的距离,单掌握沟通的例如在嵌入式的系统、 传感器和 SD 卡。设备在哪里主设备启动数据帧的主从
请点击左侧文件开始预览 !预览只提供20%的代码片段,完整代码需下载后查看 加载中 侵权举报
- 2022-03-22 00:33:48下载
- 积分:1
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用Verilog实现的中值滤波代码
在ISE下的中值滤波代码,采用的Verilog HDL语言,已经验证通过,方法简单,适合初学者使用,欢迎改进交流。。。。。。。。。。
- 2023-05-17 13:00:03下载
- 积分:1
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iic从机代码
i2C slave功能模块的一种实现方式,简单易根据自己实际需求做修改,已经过FPGA验证可以很好的工作
- 2022-04-30 08:50:00下载
- 积分:1
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AD9117芯片配置程序
说明: 实现AD9117芯片的配置功能,这是一款DAC芯片(Realize the configuration function of ad9117 chip, which is a DAC chip)
- 2020-07-07 16:58:58下载
- 积分:1
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Poiseuille_BB_solution
LBM用于Poiseuille流初学者程序,直接反弹格式(LBM Poiseuille)
- 2021-02-24 15:49:39下载
- 积分:1