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SR_DDS
DDS信号源设计,有正弦波,方波,三角波,AM波,FM波,还有PSK,FSK,16QAM等多种信号产生。(DDS signal source design, there are sine, square wave, triangle wave, AM wave, FM wave, as well as PSK, FSK, 16QAM and other signal generation.)
- 2016-03-20 22:04:51下载
- 积分:1
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ATmega128通讯口示例程序
用于ATmega128的一些通讯程序,包含I2C UART,SPI等接口,用ICCAVR编译(for ATmega128 some communications procedures, including UART I2C, SPI interfaces with ICCAVR compiler)
- 2005-03-21 11:26:08下载
- 积分:1
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ug948-design-files
Xilinx Sysgen User Guide
- 2018-10-14 21:54:22下载
- 积分:1
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spi_slave
说明: xilinx 平台的SPI从接口实现源码,供参考学习(used xilinx,slave-spi interface.)
- 2019-04-21 12:08:29下载
- 积分:1
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基于FPGA的简易流水灯,适用新手入门级训练,课程教学等
新手教学代码流水的呢,非常简单一看就懂,欢迎交流
- 2022-03-01 02:17:31下载
- 积分:1
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Verilog_code_for_AWGN
说明: verilog实现awgn信道噪声的代码,支持可变的信噪比。利用移位寄存器来实现伪随机序列。(verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence. )
- 2021-01-14 16:48:47下载
- 积分:1
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MB
说明: 基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)
- 2015-04-21 20:11:14下载
- 积分:1
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QAM16_demo
This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.
- 2010-11-09 03:00:52下载
- 积分:1
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verilog代码 cordic 核心
Cordic 核心的100%行为实现。其核心是通过高度可配置的定义。验证平台是包括在内的。请参阅详细信息包括的手册
- 2023-04-19 02:50:03下载
- 积分:1
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FIFO的verilog程序
动画电影好的颠覆活动符合大喊大吼,道光皇帝繁华的大喊大吼,给对方互动活动芳华虚度和。电饭锅很多新的,都会给读后心得黑灯瞎火大学,得到优惠电信用户读后心得颠覆活动消化道,颠覆活动符合东西方呼吸道,东方红乡读后心得银行信贷参加。
- 2022-01-24 09:57:06下载
- 积分:1