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RISC
说明: URISC的RTL级设计,Verilog代码(Design: URISC RTL Verilog)
- 2019-06-16 23:07:39下载
- 积分:1
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altera_fft
verilog实际例子,非常适合初学者学习(verilog practical examples, very suitable for beginners to learn)
- 2020-12-06 16:49:22下载
- 积分:1
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FPGA60进制数码管显示VHDL代码
FPGA设计中的60进制计数器,通过2个七段数码管系那是出来。代码简单易懂,仿真通过,而且在FPGA开发板上加载显示成功。很有用的入门代码。
- 2022-07-12 13:55:48下载
- 积分:1
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EDanDanAssistg
蛋蛋助手,可以动态配置生成代码格式,方便ORM或或程序员的生成工作 ,经测试
(Egg assistant, can be dynamically configured to generate code format, convenient ORM, or programmer generation work, tested)
- 2012-09-10 00:33:07下载
- 积分:1
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RLC Test
说明: RLC Test程序,一个电子竞赛的题目。里面有详尽的源代码。(RLC Test procedures, an electronic race issue. There are detailed source code.)
- 2005-09-04 20:58:18下载
- 积分:1
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该源码为VHDL语言编写的分频器,在W
该源码为VHDL语言编写的分频器,在W-4b教学平台上通过验证-The VHDL source for the prescaler languages, W-4b in the teaching platform validated
- 2022-01-24 14:12:26下载
- 积分:1
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20190718
说明: uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device
- 2020-06-21 21:40:01下载
- 积分:1
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设计一个可以小时、分钟、12小时或24小时和秒的时间…
设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟,并具有定时与闹钟功能,能在设定的时间发出闹铃音,能非常方便地对小时、分钟和秒进行手动调节以校准时间,每逢整点,产生报时音报时。
实验平台:
1. 一台PC机;
2. MAX+PLUSII10.1。
Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
- 2022-07-22 15:10:59下载
- 积分:1
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watch
数字钟,简单的数电应用,电子表源程序,常用也使用-watch
- 2022-04-18 14:17:50下载
- 积分:1
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shouhuoji.vhd
自动售货机程序(Vending machine procedures)
- 2008-04-05 22:08:58下载
- 积分:1