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Using FPGA realize DDS, can be frequency, amplitude from hardware to complete

于 2022-04-02 发布文件大小:659.60 kB

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用FPGA实现DDS,可变频,幅值由硬件完成-Using FPGA realize DDS, can be frequency, amplitude from hardware to complete

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ECHO_DE2
Very good info. for RS-232 echo VHDL code .

2008-05-31 00:41:53下载

积分：1
this come from alter ,you can look and find it on line about jtag.
this come from alter ,you can look and find it on line about jtag.

2022-04-26 20:24:26下载

积分：1
任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。...
任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.

2022-08-10 12:37:41下载

积分：1
nor_flash_core
Verilog实现的NOR FLASH控制器，基于M25P128开发，功能完整，简洁易懂，自用无问题。(Verilog implementations NOR FLASH controller, based M25P128 development, full-featured, easy to read, for personal use, no problem.)

2021-03-09 14:09:27下载

积分：1
DDS
基于ARM的DDS信号发生器设计，可以产生各种信号的波形，生成所需要的信号，可供实验用(DDS signal generator based on ARM, can produce a variety of signal waveform can be used for experiment)

2013-03-29 18:49:52下载

积分：1
uart
使用FPGA实现UART收发。支持多种波特率。(Using FPGA to achieve UART transceiver.)

2020-11-07 15:29:50下载

积分：1
220model
quartus 的220model 与 altera mf的库用于fpga的modelsim仿真过程中添加到工程里面(the libary of 220 model and altera mf when we simulate the fpga project by modelsim)

2020-07-04 11:00:01下载

积分：1
pci144_vhdl
PCI vhdl for Fpga designer to design PCI IP

2007-12-23 20:58:15下载

积分：1
Electronic organ program design implementation and simulation of vhdl source cod...
电子琴程序设计与仿真的vhdl实现的源代码-Electronic organ program design implementation and simulation of vhdl source code

2022-02-02 22:03:59下载

积分：1
256M_sdram_OK
改自特权同学verilog语言写sdram测试程序；支持256M内存(verilog sdram )

2013-12-23 16:15:43下载

积分：1

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Using FPGA realize DDS, can be frequency, amplitude from hardware to complete

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