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01_基于ZYNQ的FPGA基础入门
说明： VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)
- 2020-06-17 12:00:01下载
- 积分：1
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hamming_encodeadecode
用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。(Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and then error correction decoding and output, see the detailed process simulation.)
- 2011-04-22 16:46:39下载
- 积分：1
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VHDL硬件描述语言与数字逻辑电路设计
VHDL硬件描述语言与数字逻辑电路设计-VHDL hardware description language and digital logic circuit design
- 2023-03-10 23:05:04下载
- 积分：1
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HLD开发语言ADHL介绍。ADHL是ALTERA公司开发的硬件描述语言，也是一种较为流行的开发工具。是介绍AHDL的入门培训资料。...
HLD开发语言ADHL介绍。ADHL是ALTERA公司开发的硬件描述语言，也是一种较为流行的开发工具。是介绍AHDL的入门培训资料。-HLD development language ADHL introduction. ADHL is ALTERA developed hardware description language, but also a more popular development tools. AHDL is the introduction of induction training information.
- 2022-01-28 15:27:10下载
- 积分：1
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ulpi_port
ULPI UTMI conversion
- 2015-03-12 14:59:25下载
- 积分：1
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LFM
该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)
- 2021-04-19 09:38:51下载
- 积分：1
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wdt
Watch Dog Counter reset the output when the given timing meets.
- 2009-08-13 19:05:09下载
- 积分：1
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第七次课--视频图像DCT处理及水印嵌入
熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim
验证，文件中包含TEST...
altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序，已经过matlab 和modelsim
验证，文件中包含TESTBENCH ，直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
- 2022-05-31 13:50:54下载
- 积分：1
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LDPC_Encoder
verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)
- 2021-03-08 19:19:28下载
- 积分：1
