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srio
fpga平台实现srio通信，以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)
- 2017-07-09 16:52:45下载
- 积分：1
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signal-processing-matlab
信号处理中所用到的matlab程序，包括LFM,NLFM,BPSK,QPSK等等。(Matlab procedures used in signal processing, including LFM, NLFM, BPSK, QPSK, and so on.)
- 2012-11-01 00:55:18下载
- 积分：1
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卡内基梅陇大学verilog课程讲义-unlocked
verilog讲义
卡内基梅陇大学verilog课程讲义-unlocked
卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)
- 2020-06-20 18:00:02下载
- 积分：1
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shumagua
通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made into a single-chip digital clock program)
- 2013-10-27 12:30:04下载
- 积分：1
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ahb2wishbone_latest.tar
AHB to Wishbone memory interface VHDL source code
- 2013-01-11 11:17:03下载
- 积分：1
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VHDL在SOURCEINSIGHT的插件
VHDL在SOURCEINSIGHT的插件-VHDL in SOURCEINSIGHT plug-ins
- 2022-08-13 02:07:02下载
- 积分：1
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sph-original-codes
SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)
- 2020-10-22 10:27:23下载
- 积分：1
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DDR3_user_design
在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)
- 2012-02-02 15:16:00下载
- 积分：1
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UART_prj_ViHDL
vhdl project at sbu uni in iran
uart
- 2010-05-08 16:18:37下载
- 积分：1
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ODBC
ODBC编程实例，使用ODBC对基于开关量数据采集卡的通信接口设计与实现。(ODBC programming examples, using ODBC for data acquisition card based digital communications interface design and implementation.)
- 2013-07-14 13:16:35下载
- 积分：1
