DDR3_user_design

代码说明：

  在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)

文件列表：

user_design
...........\datasheet.txt,2401,2011-12-02
...........\log.txt,2345,2011-12-02
...........\mig.cgc,2081,2012-01-04
...........\mig.prj,3132,2011-12-02
...........\par
...........\...\create_ise.bat,3265,2011-12-02
...........\...\DDR3_Design.cdc,13694,2011-12-02
...........\...\DDR3_Design.ucf,10435,2011-12-02
...........\...\icon_coregen.xco,1384,2011-12-02
...........\...\ila_coregen.xco,3873,2011-12-02
...........\...\ise_flow.bat,4055,2011-12-02
...........\...\ise_run.txt,1281,2011-12-02
...........\...\makeproj.bat,28,2011-12-02
...........\...\mem_interface_top.ut,385,2011-12-02
...........\...\readme.txt,6610,2011-12-02
...........\...\rem_files.bat,7951,2011-12-02
...........\...\set_ise_prop.tcl,5135,2011-12-02
...........\...\vio_coregen.xco,1572,2011-12-02
...........\rtl
...........\...\DDR3_Design.v,42166,2011-12-02
...........\...\infrastructure.v,10746,2011-05-27
...........\...\mcb_controller
...........\...\..............\iodrp_controller.v,11430,2011-05-27
...........\...\..............\iodrp_mcb_controller.v,15423,2011-05-27
...........\...\..............\mcb_raw_wrapper.v,268315,2011-05-27
...........\...\..............\mcb_soft_calibration.v,67426,2011-05-27
...........\...\..............\mcb_soft_calibration_top.v,12826,2011-05-27
...........\...\..............\mcb_ui_top.v,113866,2011-05-27
...........\...\memc_wrapper.v,66098,2011-05-27
...........\sim
...........\...\afifo.v,6916,2011-05-27
...........\...\cmd_gen.v,31157,2011-05-27
...........\...\cmd_prbs_gen.v,10179,2011-05-27
...........\...\data_prbs_gen.v,4609,2011-05-27
...........\...\DDR3_Design.prj,1151,2011-12-02
...........\...\ddr3_model_c4.v,149785,2011-12-02
...........\...\ddr3_model_parameters_c4.vh,155864,2011-12-02
...........\...\init_mem_pattern_ctr.v,23611,2011-05-27
...........\...\isim.bat,3314,2011-12-02
...........\...\isim.tcl,3224,2011-12-02
...........\...\mcb_flow_control.v,17386,2011-05-27
...........\...\mcb_traffic_gen.v,26129,2011-05-27
...........\...\memc_tb_top.v,86783,2011-05-27
...........\...\rd_data_gen.v,11019,2011-05-27
...........\...\readme.txt,5217,2011-12-02
...........\...\read_data_path.v,15798,2011-05-27
...........\...\read_posted_fifo.v,8119,2011-05-27
...........\...\sim.do,5394,2011-12-02
...........\...\sim_tb_top.v,34726,2011-12-02
...........\...\sp6_data_gen.v,27751,2011-05-27
...........\...\tg_status.v,4732,2011-05-27
...........\...\v6_data_gen.v,122267,2011-05-27
...........\...\write_data_path.v,5751,2011-05-27
...........\...\wr_data_gen.v,11282,2011-05-27
...........\synth
...........\.....\DDR3_Design.lso,6,2011-12-02
...........\.....\DDR3_Design.prj,460,2011-12-02
...........\.....\mem_interface_top_synp.sdc,1050,2011-12-02
...........\.....\script_synp.tcl,1489,2011-12-02
...........\tmp
...........\...\_cg
...........\...\...\xil_2516_5.in,1878,2012-01-04
...........\...\...\xil_2516_5.out,18,2012-01-04