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M序列?¨
生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)
- 2019-05-05 15:54:38下载
- 积分：1
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this a fpga sparttan 3e based project in which
i have made a game based on vg...
this a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for ps/2 interface .-this is a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for ps/2 interface .
- 2022-05-21 12:25:58下载
- 积分：1
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PiSo
8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)
- 2020-11-30 21:59:27下载
- 积分：1
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classdiagramnew
class diagram diagram for AIRS
- 2015-06-10 22:44:10下载
- 积分：1
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pcm
利用VHDL语言和模块化设计实现PCM编译码的功能，整体工程和代码全有。(PCM encode and decode by VHDL in Quartus2. )
- 2020-11-02 10:39:53下载
- 积分：1
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SR_DDS
DDS信号源设计，有正弦波，方波，三角波，AM波，FM波，还有PSK,FSK,16QAM等多种信号产生。(DDS signal source design, there are sine, square wave, triangle wave, AM wave, FM wave, as well as PSK, FSK, 16QAM and other signal generation.)
- 2016-03-20 22:04:51下载
- 积分：1
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LATTICE_ASYNFIFO
LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 (LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded)
- 2013-09-09 11:10:01下载
- 积分：1
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Three
Three-input Majority Voter
-- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
-Three-input Majority Voter -- The entity declaration is followed by three alternative architectures which achieve the same functionality in different ways.
- 2022-08-12 06:51:37下载
- 积分：1
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Time_setting
时间设置 可以作为设计中的一个小模块进行使用 方便快捷(time setting)
- 2012-03-30 10:12:28下载
- 积分：1
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明白4
实现了一个四层单电梯控制系统。门可以自动开关，也可以手动开关。代码可以集成，不超过驱动的现象。
- 2022-04-10 00:20:47下载
- 积分：1
