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wp_max_flash
FPGA中FLASH配置控制源码,VHDL和Verilog(FPGA source code in the FLASH configuration control, VHDL and Verilog)
- 2007-12-11 15:57:15下载
- 积分：1
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cic_dec_8_three
CIC 文件的ＶＨＤＬ
cic_dec_8_three
CIC 文件的ＶＨＤＬ-cic_dec_8_threeCIC documents VHDL
- 2023-03-30 12:50:03下载
- 积分：1
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基于vhdl开发的频率发生器
基于vhdl开发的频率发生器-Based on the development of frequency generator vhdl
- 2022-08-19 15:44:18下载
- 积分：1
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dadishu_v1
VHDL实现简单打地鼠游戏机，北邮数电实验(VHDL simple playing hamster games, BUPT number of electric experiment)
- 2020-11-03 13:29:52下载
- 积分：1
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Xilinx公司Accel DSP项目
xilinx accel dsp实例项目工程-xilinx accel dsp project
- 2023-03-09 20:10:02下载
- 积分：1
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histogram_new
Verilog语言描述，统计图片的像素值直方图(Verilog，Pictures of the pixel value histogram statistics)
- 2021-03-04 17:39:31下载
- 积分：1
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password
verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)
- 2011-10-18 21:45:45下载
- 积分：1
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rs-codec(255-223)
这是rs（255，223）编码的verilog源程序。里面有：encode、decode、test－bench等文件。(This is rs (255,223) verilog source coding. Inside : encode, decode, test-bench and other documents.)
- 2021-05-13 00:30:02下载
- 积分：1
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Wishbone dma ip core
Wishbone dma ip core
- 2022-01-26 04:18:15下载
- 积分：1
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GMSK调制基带眼图仿真源代码
GMSK调制基带眼图仿真源代码，基于MATLAB(GMSK modulation baseband eye diagram simulation source code, based on MATLAB)
- 2020-06-28 11:40:01下载
- 积分：1
