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67_ellipf
vhdl very good debug release vhdl very good debug release
- 2006-10-22 18:39:48下载
- 积分：1
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08_4_hdmi_loop
HDMI做为视频输出输入接口已经广泛使用很长时间，主要通过TMDS差分编码传输。本实验通过在HDMI屏幕上显示彩条和输入输出环通实验，来练习视频的时序和视频颜色的表示，为后面视频处理实验做个基础。(HDMI as video output input interface has been widely used for a long time, mainly through TMDS differential coding transmission. In this experiment, by displaying color bars and input/output loop experiments on HDMI screen, video timing sequence and video color representation are practiced to lay a foundation for video processing experiments later)
- 2020-06-17 09:00:02下载
- 积分：1
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verilog三阶数字锁相环
输入信号为bpsk信号，载波中频为5Mhz，多普勒为10k，接收机三阶锁相环实现对bpsk调制信号的载波进行复制和跟踪,
- 2023-01-30 05:45:03下载
- 积分：1
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clock
Quartus II软件设计数字电子钟，使用verilog语言编写各个
模块生成symbol files，再用原理图方式制作顶层文件。
完成的功能有：能够显示时、分、秒；具有清零，调节分钟的功能；
具有整点报时功能，声响电路发出叫声；
(failed to translate)
- 2013-05-07 10:11:31下载
- 积分：1
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pipelined_fft_256
说明： 256 点fft的verilog source codec以及testbench(256 point fft, with verilog source codec and testbench)
- 2019-11-02 14:16:07下载
- 积分：1
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C-V2X-master
说明： LTE is an abbreviation for Long Term Evolution.
- 2019-06-29 01:08:09下载
- 积分：1
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74-Hamming-code-encoder-and-decoder
基于VHDL实现（7，4）汉明码的编码器和译码器(VHDL-based implementation (7,4) Hamming code encoder and decoder)
- 2011-06-09 20:47:07下载
- 积分：1
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ad0809
对ad0809的控制代码( ad0809control)
- 2010-08-28 15:00:50下载
- 积分：1
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Fast_median_filter
说明： FPGA数字图像处理实现均值滤波，并且仿真将生成图片写出TXT格式以便使用MATLAB查看(Mean filter is realized by digital image processing in FPGA, and the generated image is written in TXT format for viewing with MATLAB.)
- 2019-06-01 21:23:25下载
- 积分：1
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16QAM-modulation-based-on-FPGA
基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)
- 2014-05-07 14:05:25下载
- 积分：1
